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**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
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**82C546/547 Python PTM3V c:94
***Notes:...
***Info:...
***Configurations:...
***Features:
o 100% PC/AT compatible
o Fully supports the 3.3V/5.0V Pentium processors
o Three chip solution:
- 82C547 System Controller (SYSC) (160-pin PQFP)
- 82C546 AT Bus Controller (ATC) (208-pin PQFP)
- 82C206 Integrated Peripheral Controller (IPC) (84-pin PLLC
or 100-pin PQFP)
o Two buffer/translator support chips:
- 82C606A (100-pin PQFP)
- 82C606B (100-pin PQFP)
o Supports Pentium CPU address pipelining
o 1X clock source, supporting systems running Pentium processor
bus clocks up to 60MHz
o Write-back, direct-mapped cache with size selections:
64KB, 128KB, 256KB, 512KB, 1MB and 2MB
o Programmable cache write policy: write-back or write-through
o Fully programmable cache and DRAM read/write cycles
o Supports 3-2-2-2 cache burst read cycles at 60MHz
o Built-in tag auto-invalidation circuitry
o Support for two programmable non-cacheable memory regions
o Options for cacheable, write-protected, system and video BIOS
o Supports two banks of 64-bit wide DRAMs with 256KB, 512KB, 1MB
2MB, 4MB and 8MBx36 Page Mode
o Supports DRAM configurations up to 128MB
o Supports 3-3-3-3 pipeline DRAM burst cycles
o DRAM post write buffer
o Support for flash ROM
o Shadow RAM option
o Hidden refresh with CAS-before-RAS refresh supported
o High-performance 32-bit local bus support
o Performance-oriented snoop-line comparator for VL/ISA
bus masters
o External DMA page register
o Turbo/slow speed selection
o Asynchronous CPU and VL bus interface
o AT bus clock speed programmability
o Transparent 8042 emulation for Fast CPU Reset and GATEA20
generation
o Supports Ports 92h, Gate A20, and Fast Reset
o Mixed voltage (3.3V and 5.0V), low-power, high speed, 0.8
micron CMOS technology
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
**VT82C580VP Apollo VP, Pentium/M1/K5 PCI/ISA System <02/15/96
***Info:
The VT82C580VP Apollo-VP is a high performance, cost-effective and
energy efficient chip set for the implementation of PCI/ISA desktop
and notebook personal computer systems based on the 64-bit
P54C/Pentium/K5/M1 super-scalar processors. CPU and cache interface is
supported up to 66Mhz CPU external bus speed (with CPU internal speed
up to 200Mhz and above). The CPU, DRAM and PCI bus are all
independently powered so that each of the bus can be run at 3.3v or
5v, independently. The ISA bus always runs at 5v.
The VT82C580VP chip set consists of the VT82C585VP system controller,
the VT82C586 PCI to ISA bridge, and two instances of the VT82C587VP
data buffers. The CPU bus is minimally loaded with only the CPU,
secondary cache and the chip set. The VT82C587VP data buffers isolate
the CPU bus from the DRAM and PCI bus so that CPU and cache operation
may run reliably at the high frequencies demanded by today's
processors. The VT82C585VP contains arbitration logic to support the
UMA (unified memory architecture) with video/GUI products from major
video vendors. Multiple deep FIFOs (thirty-two double words) are
included between multiple data paths to allow efficient concurrent
operation and DRAM utilization. The VT82C586 PCI to ISA bridge
includes integrated 206-style IPC (DMA, interrupt controller and
timer), integrated keyboard controller with PS2 mouse support,
integrated DS12885 style real time clock with extended 128 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter
and gather capability, and integrated USB (universal serial bus)
interface with root hub and two function ports with built-in physical
layer transceiver. A complete main board can be implemented with only
six TTLs. Please refer to Figure 1 [see datasheet] for the system
block diagram.
***Configurations:...
***Features:...
**VT82C580VPX Apollo VPX, VPX/97, Pentium with 66/75MHz Bus <01/09/97...
**VT82C590 Apollo VP2, VP2/97, Single-Chip Pentium 66MHz <01/10/97...
**VT82C597/AT Apollo VP3, Single-Chip for Pentium with AGP <10/03/97...
**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97...
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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