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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in the configurations section  and below have been sourced
from the second.

"Although the 82497 Cache Controller  is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache  Controller is part  of the  Pentium Processor  (510\60, 567\66)
Chip  Set, the  two parts  are functionally  identical except  for the
differences noted in this section." - p491

Aside  from some  minor  differences in  pin  configuration, the  main
difference is the direct support  for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.


This  chip was  used on  the Pentium  90MHz CPU  complexes of  Intel's
Xpress  platform.   Specifically  the BXCPUPENT90  (Single  90MHz,  16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.

***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Wait States at 66 MHz 
    - Two-Way Set Associative 
    - Writeback with MESI Protocol 
    - Concurrent CPU Bus and Memory Bus Operation 
    - Boundary Scan
o   Pentium Processor (735\90, 815\100)
    - Chip Set Version of Pentium Processor (735\90, 815\100) 
    - Superscalar Architecture -
    - Enhanced Floating Point 
    - On-Chip 8K Code and 8K Data Caches
    - See Pentium Processor Family Data Book for More Information
o   Highly Flexible
    - 256K to 512K with Parity
    - 32-, 64-, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o   Full Multiprocessing Support
    - Concurrent CPU, Memory Bus and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read For Ownership, Write-Allocation and Cache-to-Cache
      Transfers

**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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