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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**82C496/7       DXBB PC/AT Chipset (Cached)                 <01/16/92
***Info:...
***Configurations:...
***Features:
o   386 and 486 CPU interface
o   Isolates the CPU bus from Local bus, more reliable system
    operation at high speed
o   Asynchronous handshaking between CPU bus and Local bus; fixed 
    base-board speed with upgradeable CPU card speed
o   Direct map write back cache with one level write buffer and
    16-byte line size
o   Programmable 2-1-1-1, 3-1-1-1, 2-2-2-2 or 3-2-2-2 burst read cycle
o   Programmable cache write hit 0 or 0 wait state
o   Optional Dirty bit
o   Supports 32K - 256K cache size for 386 cache system
o   Supports 64K - 512K cache size for 486 cache system
o   Provides TAG and Dirty RAM test capability
o   Built-in TAG auto-invalidation circuitry
o   Two programmable non-cacheable regions
o   Option for write-protected, cacheable Video BIOS
o   Cacheable AT bus memory space
o   8042 emulation for fast CPU-reset and gate A20 generation
o   1X clock source support for systems from 16 MHZ to 50 MHZ
o   160-pin plastic quad flat package

**82C498         DXWB PC/AT chipset [no datasheet]                   ?...
**82C499         DXSC DX System Controller                        c:93...
**82C546/547     Python PTM3V                                     c:94...
**82C556/7/8     Viper [no datasheet]                                ?...
**82C556/7/8N    Viper-N  Viper Notebook Chipset             <05/25/95...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C852     Multi I/O For XT                                    <91
***Info:
The  Multi-I/O  chip, UM82C852  is  an  integrated  chip of  UM82C450,
UM82C11, UM82C8167. This  chip is a Multi-I/O for  PC/XT and PS2 model
30.

The   82C450  asynchronous   communications  element   (ACE)  performs
serial-to-parallel  conversion   on  data  characters   received  from
peripheral  devices or  modems, and  parallel-to-serial  conversion of
data characters transmitted by the CPU. The complete status of the ACE
can  be read  at  any time  during  functional operation  by CPU.  The
information obtained  includes the type and condition  of the transfer
operations being performed and error conditions.

The  82C11  parallel  port  provides  the user  with  a  bidirectional
parallel data  port that fully  supports the parallel  Centronics type
printer.

The 82C8167 real time clock includes an addressable real time counter,
56 bits  of static RAM with  an on chip oscillation  circuit which can
generate the 32,768 Hz time base.

The 82C852 is packaged in a 68-pin plastic leaded chip carrier.
***Versions:...
***Features:...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
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