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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
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*UMC...
**UM82C210     386SX/286 AT Chip Set                               <91
***Info:
The  UM82C210 is  an enhanced  PC/AT compatible  chip set  which  is a
highly integrated VLSI implementation of the control logic used in the
IBM AT. Due to its flexible architecture, the UM82C210 can be used, in
any  80286 based  systems.  The  UM82C210 chip  set consists  of three
chips  which  are:  UM82C211  (System  Controller),  UM82C212  (Memory
Controller), and UM82C215 (Data /Address Buffer).

The UM82C211,  System controller, provides all control  signals for AT
bus   including  bus   synchronization.  In   order  to   meet  timing
requirements  for different peripheral  boards, the  UM82C211 provides
programmable command delays and wait states.

The  UM82C212, Memory  Controller, provides  both  conventional memory
access and Page  Interleaved memory access. The UM82C212  also has LIM
EMS features that  support up to 8 MB of  on-board DRAMs. In addition,
the Shadow  RAM feature of  the UM82C212 allows faster  execution BIOS
codes.

The  UM82C215, Data/Address  Buffer, provides  buffering  and latching
functions between address buses and  data buses. It also generates the
parity bit and detects parity errors.

***Configurations:...
***Features:...
**UM82C3xx     Twinstar & UM82C336F/N & UM82C39x [no datasheet]      ?...
**UM82C380     386 HEAT PC/AT Chip Set                             <91...
**UM82C480     386/486 PC Chip Set                                 c91...
**UM82C493/491 ??????????????? [no datasheet]                        ?...
**UM8498/8496  486 VL Chipset  "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886  HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890       Pentium chipset [no datasheet]                        ?...
**
**Support Chips:
**UM82152      Cache Controller (AUStek A38152 clone)              <91...
**UM82C852     Multi I/O For XT                                    <91...
**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
**Other chips:...
*Unresearched:...
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*ZyMOS...
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