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**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00
Chips:
[82815] (GMCH) [82801AA] (ICH) [82802] (FWH) i754 AGP (Coloma)
CPUs: P-III/P-III(T)*1/Celeron
DRAM Types: SDRAM PC133*2
Mem Rows: 6*3
DRAM Density: 64Mbit 128Mbit 256Mbit
Max Mem: 512MB
ECC/Parity: No
AGP speed: 1x 2x 4x
Bus Speed: 66 100 133
PCI Clock/Bus: 1/2 1/3 1/4 PCI 2.2
>*1 P-III Tualatin first supported from B-0 stepping of chipset.
>*2 FSB and DRAM can be asynchronous. At 66MHz FSB, and 100MHz FSB,
DRAM operates at 100MHz. At 133MHz FSB, DRAM can be set to 100 or
133MHZ.
>*3 Supports 3 double-sided DIMMs @ 100MHz, 2 at 133MHz.
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
**GC101/102/103 12/16MHz PC/AT Compatible Chip Set + EMS 4.0 c:Jul89
***Notes:...
***Info:...
***Configurations:...
***Features:...
**GCK113 80386 AT Compatible Chip Set c:oct89...
**GCK181 Universal PS/2 Chip Set c:Mar89...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
**UM82C230 286AT MORTAR Chip Set <91
***Info:
The UMC's MORTAR (286AT) Chip Set UM82C230 series provides an economic
alternative for building a reliable IBM PC/AT compatible system. A
commercial 12MHZ/0 wait state, 4MByte main memory system and
math-coprocessor can be easily built by using 3 VLSIs, 8 logic
components plus memory and processor.
The UM82C230 MORTAR chipset consists of the UM82C231 System/Memory
Controller, the UM82C232 Data/Address Buffer and the UM82C206
Integrated Peripherals Controller (IPC).
As shown in the System Block Diagram, [see datasheet] there are three
data buses: local data bus, AT data bus and peripheral data (XD) bus.
The local DRAM, EPROM and Numerical Processor are located on the local
data bus. The UM82C206 and 8042 Keyboard Controller sit on the XD bus.
The AT data bus was driven by the UM82C232 directly which conveys the
data to/from the AT Channel Adaptors.
The address bus architecture is also very simple; local CPU address
bus, local DRAM address bus (MA), peripheral address bus (XA) and AT
address bus. The local address bus is shared between CPU, UM82C231 and
UM82C206. The MA bus is used by the local DRAM only. Most of the
system board devices are attached to the XA bus, like UM82C232,
UM82C206, ROMs and 8042. Some AT address lines are driven by the
UM82C231 or UM82C232 directly; the others are buffered.
The UM82C231 provides synchronization and control signals for all
buses. The UM82C231 also distinguishes if the current cycle is local
memory cycle. Upon detecting that it is a local DRAM cycle, no AT
control signals are sent out to the AT channel. The UM82C231 is based
on the memory configurations to complete the current cycle with
fastest response. If the cycle is AT cycle, the UM82C231 sends out the
control signals sequentially which are then used by the adaptors or
system board devices to receive the write data or to send the fetched
data. Then, depending on the status signals sent back by the adaptors
or system board devices, the UM82C231 determines which kind of AT
cycles to perform: 8-bit, 16-bit, bus conversion, wait state insert,
or wait state cycle.
The UM82C232 Data/Address buffer provides the buffering and latching
between the CPU local data bus, AT bus and XD bus. The parity bit
generation and parity bit checking logic resides in the UM82C232 also.
During DMA cycles, the UM82C232 latches the address from XD, which is
sent by the UM82C206, and transfers to XA bus.
***Configurations:...
***Features:...
**UM82C210 386SX/286 AT Chip Set <91...
**UM82C3xx Twinstar & UM82C336F/N & UM82C39x [no datasheet] ?...
**UM82C380 386 HEAT PC/AT Chip Set <91...
**UM82C480 386/486 PC Chip Set c91...
**UM82C493/491 ??????????????? [no datasheet] ?...
**UM8498/8496 486 VL Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8881/8886 HB4 PCI Chipset "Super Energy Star Green"[no dsheet]c94...
**UM8890 Pentium chipset [no datasheet] ?...
**
**Support Chips:
**UM82152 Cache Controller (AUStek A38152 clone) <91...
**UM82C852 Multi I/O For XT <91...
**UM82C206 Integrated Peripheral Controller <91...
**UM82c45x Serial/Parallel chips ?...
**Other chips:...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
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