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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf

Information taken from: 
            1995_Intel_Pentium_Processors_and_Related_Components.pdf*
                                         8249x Cache controllers.pdf**
>*  Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95

The info and features section have  been solely sourced from the first
source.   The  second source  provides  far  more detail.   Additional
information in  the configurations section  has been sourced  from the
second.

Difference to 82497/492 is this supports 1 Mbyte to 2 Mbyte cache.

***Info:...
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma)       05/06/96...
***440LX (Balboa)       08/27/97...
***440BX (Seattle)      c:Apr'98...
***440DX (?)            c:?...
***440EX (?)            c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?)          05/17/99...
***440MX (Banister)     05/17/99...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91
***Notes:
InfoWorld Oct 28, 1991 p38:
"...Unlike earlier EISA chip sets, Ti's Tact84500 is comprised of only
four VLSI chips for controlling the bus, memory, peripherals, and data
path unit. The Tact unit can also control eight EISA bus masters along
with DRAM and a single-layer  EISA-bus write buffer.  According to TI,
the suggested  price of the  EISA chip set,  at $130 in  quantities of
100, should  make EISA-based  systems price competitive  with existing
ISA-based systems."

At least one of the chips is called 84542. This is probably the memory
controller.



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