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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
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**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91
***Info:
The SL82C465 cache controller supports both 1X and 2X clock modes. The
1X clock  mode means that the CCLK2  signal is used as  the CPU clock;
the 2X clock  mode means that the PCLK signal  (half the frequency and
the phase indicator  of CCLK2) is used as the  CPU clock. The SL82C465
and other CPU local bus devices run at the same clock frequency as the
CPU, while  the rest of the system  runs at the frequency  of PCLK. In
other words, the operating frequency of the system logic is either the
same (2X clock mode) or half the speed of the CPU (1X clock mode). For
the 1X clock mode, the timing of the signals between the CPU/Cache and
the system logic interface  is converted by the SL82C465 automatically
to  satisfy  the requirement  of  individual  clocks.  Table 1-1  [see
datasheet] lists  the operating frequencies  of the CPU local  bus and
the system logic with the oscillator used.

The 2X  clock mode is recommended  for a CPU frequency  no faster than
33Mhz because the system logic  is available at the targeted speed and
the  performance  is  slightly  better  than if  1X  clock  mode  were
used. For  a CPU  frequency faster  than 33Mhz, the  1X clock  mode is
preferred  for  486  systems  because  it  becomes  increasingly  more
difficult to  build a reliable  system with an oscillator  faster than
66Mhz.

***Versions:...
***Features:...
*TI (Texas Instruments)...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89
***Info:...
***Configurations:...
***Features:
o   High-Speed 1-um CMOS Technology Supports System Speeds up to 
    33 MHz
o   Fully AT-Compatible 386 Three-Chip SX, Four-Chip DX Solutions
o   Only Four Additional Logic Chips Needed
o   Major Features Programmable Through Software
o   TACT83442 Memory Control Unit (MCU)
    - Cascadable up to Eight Devices
    - Address Range of up to 32M Byte Per Device, 256M Byte Fully 
      Cascaded
    - Supports 256K-, 1M-, and 4M-Bit DRAMs in Normal, Page, Word-
      interleave, and Page Block-interleave Modes
    - Programmable DRAM Timing Parameters
    - Supports up to Two Memory Banks for 32-Bit Systems and Four 
      Banks for 16-Bit Systems
    - Can Directly Drive up to 36 DRAM Devices
    - Shadow RAM Available Between 0C 0000h and 0F FFFFh
    - Contains Global Page Mapping RAM Allowing Remap of 
      - 64K-Byte Memory Blocks Above 1M Byte
      - 16K-Byte Memory Blocks Below 1M Byte
o   TACT83443 AT Bus Interface Unit (ATU)
    - Internal Clock Switching Between Two Independent Frequencies 
      Controlled by Software
    - Asynchronous AT Bus Interface With Write Buffer Option
    - Full AT Direct-Drive Capability
    - Extended Direct Memory Access Mode for 32-Bit Operation
    - Fast CPU Reset and A20 GATE Modification
    - Numeric Processor Interface for 387SX, 387DX, and Weitek 3167
    - Integrates All Essential AT Peripherals
    - Real Time Clock With 128-Byte CMOS RAM
o   TACT83441 Data Path Unit (DPU)
    - 8- and 16-Bit Data Bus Sizing
    - Data Path Cascadable to 32 Bits
    - Write Buffer Capability for AT Bus Access
    - Supports Posted Write Operations From Cache Controller
    - Parity Generation and Checking Logic

**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
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