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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory bus controller, provide a second-level
cache subsystem that eliminates the memory latency and bandwidth
bottleneck for a wide range of multiprocessor systems based on the
i860 XP microprocessor. The CPU interface is optimized to serve the
i860 XP microprocessor with zero wait states at up to 50 MHz. A
secondary cache built from the 82495XP and 82490XP isolates the CPU
from the memory subsystem; the memory can run slower and follow a
different protocol than the i860 XP microprocessor.
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*SIS...
**5501/5502/5503 Pentium/P54C PCI/ISA Chipset <04/02/95
***Info:...
***Configurations:...
***Features:...
**5511/5512/5513 Pentium PCI/ISA <06/14/95...
**5571 (Trinity) Pentium PCI/ISA Chipset (75MHz) <12/09/96...
**5581/5582 (Jessie) Pentium PCI/ISA Chipset (75MHz) <04/15/97...
**5591/5592/5595 (David) Pentium PCI A.G.P. Chipset <01/09/98...
**5596/5513 (Genesis) Pentium PCI Chipset <03/26/96...
**5597/5598 (Jedi) Pentium PCI/ISA Chipset <04/15/97...
**530/5595 (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98...
**540 (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x SoC (System-on-chip) <03/14/02...
**
**Support chips:
**85C206 Integrated Peripheral Controller [no datasheet] ?...
**5595 Pentium PCI System I/O <12/24/97...
**950 LPC I/O <07/16/99...
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*TI (Texas Instruments)...
**TACT83000 AT 'Tiger' Chip Set (386) c89
***Info:
The Texas Instruments TACT83000 AT Chip Set is designed for cached and
noncached 386-based PC-AT compatible systems running at speeds up to
33 MHz. Manufactured with high-speed 1-um CMOS EPIC technology, the
chip set is functionally partitioned into three devices: the TACT83443
AT Bus Interface Unit (ATU), the TACT83442 Memory Control Unit (MCU),
and the TACT83441 Data Path Unit (DPU). The ATU is packaged in a
208-lead plastic quad flatpack (QFP), while the MCU and DPU are
packaged in 100-lead plastic QFPs
These three chips, along with four other logic chips, comprise all the
logic necessary for a fully compatible 16-bit 3868X-based system.
Since one DPU provides a 16-bit data path, a 32-bit 386DX-based system
requires an additional DPU.
With software-controlled configuration registers on board the ATU and
MCU, the chip set supports a wide variety of PC system config-
urations. For complete programming details, see the TACT8300 AT Chip
Set User’s Guide, literature number SRZU001.
***Configurations:...
***Features:...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
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