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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91
***Info:...
***Configurations:...
***Features:
o   Single Chip 803868X/286 PC/AT Compatible Solution for CPU Clock 
    Speeds to 2SMHz
o   SX Mode or 286 Mode
o   Supports up to 20 MB DRAM using 4M, 1M or 256K Devices in by 1 
    or 4 configuration
o   Page Mode and 2-Way Interleaving
o   LIM EMS 4.0 Support in Hardware using 2 Sets of 32 EMS Registers
o   8-Bit or 16-Bit BIOS Support
o   High Performance DRAM Multiplexed Interleave Mode
o   Asynchronous AT Bus Clock
o   Supports up to 12 MHz Backplane Operation
o   Programmable DRAM Timing
o   Port 92 Alternate GATEA20 and Hot Reset
o   Shadow RAM support over entire 640K to 1M range in 16K increments
o   BIOS Shadow support in 64K increments
o   Built-in Sleep Mode
o   Three-state control pins for board level testing
o   HCMOS Technology

**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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*TI (Texas Instruments)...
**TACT83000   AT 'Tiger' Chip Set (386)                            c89
***Info:
The Texas Instruments TACT83000 AT Chip Set is designed for cached and
noncached 386-based  PC-AT compatible systems running at  speeds up to
33 MHz.  Manufactured with high-speed  1-um CMOS EPIC  technology, the
chip set is functionally partitioned into three devices: the TACT83443
AT Bus Interface Unit (ATU),  the TACT83442 Memory Control Unit (MCU),
and the  TACT83441 Data  Path Unit  (DPU).  The ATU  is packaged  in a
208-lead  plastic quad  flatpack  (QFP),  while the  MCU  and DPU  are
packaged in 100-lead plastic QFPs

These three chips, along with four other logic chips, comprise all the
logic  necessary for  a  fully compatible  16-bit 3868X-based  system.
Since one DPU provides a 16-bit data path, a 32-bit 386DX-based system
requires an additional DPU.

With software-controlled configuration registers  on board the ATU and
MCU,  the  chip set  supports  a wide  variety  of  PC system  config-
urations.  For complete programming  details, see the TACT8300 AT Chip
Set User’s Guide, literature number SRZU001.

***Configurations:...
***Features:...
**TACT84500   AT Chip Set (486, EISA) [no datasheet, some info]    c91...
**Other:...
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