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**M????          Genie, Quad Pentium  [no datasheet, some info]    c95
***Notes:...
**M1451/49       Aladdin    (Pentium) [no datasheet]                 ?...
**M1511/12/13    Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23       Aladdin III       50-66MHz                     <Nov96...
**M1531/33/43    Aladdin IV & IV+  50-83.3MHz                <05/28/97...
**M1541/42/33/43 Aladdin V & V+    50-100MHz                         ?...
**M1561/43/35D   Aladdin 7 ArtX    [no datasheet, some info]  11/08/99...
**M6117          386SX Single Chip PC                              <97...
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**M1535/D        South Bridge                                        ?...
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**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:
o   50 MHz Intel486 DX CPU 
    - RISC Integer Core with Frequent Instructions Executing in One 
      Clock
    - 160 Mbyte/Sec Burst Bus
    - 41 Dhrystone MIPs
    - 11.5M Double Precision Whetstones/Sec.
    - On-Chip Cache and FPU
o   Highly Flexible
    - Supports 128 Kbyte and 256 Kbyte Configurations
    - Complete MESI Protocol Support
    - 32- or 64-Bit Memory Bus Width
    - Synchronous, Asynchronous, and Strobed Memory Bus Protocols
    - Variable Cache Line Sizes and Sectoring
    - Cache Data Parity Option
o   High Performance Second Level Cache
    - Two-Way Set Associative
    - Write-Back or Write Through Cache
    - Zero Wait State Cache Access
    - Concurrent CPU Bus, Memory Bus, and Internal Array Operation
o   Full Multiprocessing Support
    - Implements MESI Write-Back Cache Protocol
    - Low Bus Utilization
    - Automatically Maintains 1st Level Cache Consistency
    - Supports Read-for-Ownership, Write-Allocation, and Cache-to-
      Cache Transfers

**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91
***Info:
The SL82C465 cache controller supports both 1X and 2X clock modes. The
1X clock  mode means that the CCLK2  signal is used as  the CPU clock;
the 2X clock  mode means that the PCLK signal  (half the frequency and
the phase indicator  of CCLK2) is used as the  CPU clock. The SL82C465
and other CPU local bus devices run at the same clock frequency as the
CPU, while  the rest of the system  runs at the frequency  of PCLK. In
other words, the operating frequency of the system logic is either the
same (2X clock mode) or half the speed of the CPU (1X clock mode). For
the 1X clock mode, the timing of the signals between the CPU/Cache and
the system logic interface  is converted by the SL82C465 automatically
to  satisfy  the requirement  of  individual  clocks.  Table 1-1  [see
datasheet] lists  the operating frequencies  of the CPU local  bus and
the system logic with the oscillator used.

The 2X  clock mode is recommended  for a CPU frequency  no faster than
33Mhz because the system logic  is available at the targeted speed and
the  performance  is  slightly  better  than if  1X  clock  mode  were
used. For  a CPU  frequency faster  than 33Mhz, the  1X clock  mode is
preferred  for  486  systems  because  it  becomes  increasingly  more
difficult to  build a reliable  system with an oscillator  faster than
66Mhz.

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