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**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
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**82C546/547 Python PTM3V c:94
***Notes:...
***Info:...
***Configurations:...
***Features:
o 100% PC/AT compatible
o Fully supports the 3.3V/5.0V Pentium processors
o Three chip solution:
- 82C547 System Controller (SYSC) (160-pin PQFP)
- 82C546 AT Bus Controller (ATC) (208-pin PQFP)
- 82C206 Integrated Peripheral Controller (IPC) (84-pin PLLC
or 100-pin PQFP)
o Two buffer/translator support chips:
- 82C606A (100-pin PQFP)
- 82C606B (100-pin PQFP)
o Supports Pentium CPU address pipelining
o 1X clock source, supporting systems running Pentium processor
bus clocks up to 60MHz
o Write-back, direct-mapped cache with size selections:
64KB, 128KB, 256KB, 512KB, 1MB and 2MB
o Programmable cache write policy: write-back or write-through
o Fully programmable cache and DRAM read/write cycles
o Supports 3-2-2-2 cache burst read cycles at 60MHz
o Built-in tag auto-invalidation circuitry
o Support for two programmable non-cacheable memory regions
o Options for cacheable, write-protected, system and video BIOS
o Supports two banks of 64-bit wide DRAMs with 256KB, 512KB, 1MB
2MB, 4MB and 8MBx36 Page Mode
o Supports DRAM configurations up to 128MB
o Supports 3-3-3-3 pipeline DRAM burst cycles
o DRAM post write buffer
o Support for flash ROM
o Shadow RAM option
o Hidden refresh with CAS-before-RAS refresh supported
o High-performance 32-bit local bus support
o Performance-oriented snoop-line comparator for VL/ISA
bus masters
o External DMA page register
o Turbo/slow speed selection
o Asynchronous CPU and VL bus interface
o AT bus clock speed programmability
o Transparent 8042 emulation for Fast CPU Reset and GATEA20
generation
o Supports Ports 92h, Gate A20, and Fast Reset
o Mixed voltage (3.3V and 5.0V), low-power, high speed, 0.8
micron CMOS technology
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
**SL82C550 'Rossini' Pentium [no datasheet] c:95
***Notes:
from:
http://www.os2forum.or.at/english/info/os2hardwareinfo/pci_chips.html
The Symphony "Rossini" Chipset (Symphony Labs: 10AD/4269) (9/13/95)
This is apparently a low-cost alternative to the Triton chipset, as it
operates with up to 66 MHz external clock rates, up to two CPUs,
pipelined or non-pipelined, synchronous or [conventional] asynchronous
SRAM cache, EDO RAM, and does dual-port busmastering IDE. It will,
apparently, adjust the voltages to its various (CPU, PCI, cache, RAM)
buses to suit their requirements, and will control up to six PCI
masters. It consists of the SL82C551 cache/memory controller, the
SL82C522 data path controller, and the SL82C555 system I/O controller.
***Configurations:...
**
**Support Chips:
**SL82C365 Cache Controller (for 386DX/SX) c:91...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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