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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*OPTi...
**82C381/382 HiD/386 (386DX) c:89
***Info:
The HiD/386 Chipset, 82C381 and 82C382D, support high integration
implementations of Direct Mapped Cache with 32KB/64KB/128KB Cache for
25 and 33 MHz 386/AT Personal Computers. Combined with the 82C206
Integrated Peripherals Controller, it integrates the 386/AT mother-
board to under 20 devices, plus memory. It is designed to cost reduce
discrete and CHIPS’CS8230 based 82385 Cache 386/AT designs, as well as
boost the performance of these designs to 33 MHz, with >64KB Cache.
The 82681 provides system control logic and data bus conversion logic.
The control logic consists of 386 CPU control logic, AT Bus cycle
control, 387 Numeric Processor control logic, synchronous clock divide
logic and control of the local peripheral bus. The data bus conversion
logic consists of various 8, 16, 32 bit conversions for ROM cycles, AT
bus cycles and memory cycles.
The 820382D performs the Memory Management functions for the HiD/AT
chipset. It is designed to optimize cost of high performance 386/AT
systems with 64KB, l28KB or larger Direct Mapped Cache Memory. It also
implements logic to maintain compatibility in the AT environment . It
provides a Page Interleave backend for main DRAM memory, in order to
improve performance during miss cycles. It also has features for
reducing system cost.
It minimizes Cache Memory cost by allowing the use of slow SRAM; by
supporting single EPROM BIOS configurations; putting DRAM on the local
bus and consequently reducing DRAM speeds by 15ns typically; and by
remapping 256K of DRAM between 640K and 1024K to top of main memory.
It provides a very flexible implementation of paging for the main DRAM
memory. For even bank configurations, it provides 2-way or 4-way
interleaving; for odd banks it provides paging. This provides a
flexible approach to increasing the size of the local memory as
software demands increase, without imposing a penalty on performance.
Finally, memory performance is optimized by shadow RAM techniques for
BIOS ROMs; concatenated pages for multiple hank configurations; paging
for odd banks; and variable page size for larger DRAMs.
System Architecture
The HiD/AT chipset is compatible with the 82C206 Integrated
Peripherals Controller. Consequently, with the 82C206, a very high
integration and very high performance 386/AT can be implemented. A
typical motherboard can be designed with less than 20 devices plus
memory.
For larger AT designs, targeted at file-servers and departmental
computers, designs with 8 or more slots can be supported with external
AT bus drivers.
***Configurations:...
***Features:...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**950 LPC I/O <07/16/99
***Info:...
***Versions:...
***Features:
o Low Pin Count Interface
- Comply with Intel LPC Interface Specification Rev. 1.0
(Sept. 29, 1997)
- Supports Serial IRQ Protocol
- Supports PCI PME# Interface
o PC98/PC99, ACPI Compliant
- PC98 & PC99 compliant
- Register sets compatible with "Plug and Play ISA Specification
Rev. 1.0a"
- ACPI V. 1.0 compliant
- Supports 9 logical devices
o Enhanced Hardware Monitor
- Built-in 8-bit Analog to Digital Converter
- 3 thermal inputs from remote thermistors or thermal diode or
diode-connected transistor
- 8 voltage monitor inputs (VBAT is measured internally.)
- WatchDog comparison of all monitored values
o Fan Speed Controller
- Provides Fan ON/OFF and PWM control
- 3 programmable Pulse Width Modulation (PWM) Fan control outputs
- Each PWM output supports 128 steps of PWM modes
- Monitors 3 Fan tachometer inputs
o Game Port
- Built-in 558 quad timers and buffer chips
- Supports direct connection of two joysticks
- Game port signals are multiplexed with GPIOs
o Two 16C550 UARTs
- Supports two standard Serial ports
- UART1 is dedicated for Serial port
- UART2 supports either Serial Port or IrDA 1.0/ASKIR
o Consumer Remote Control (TV remote) IR with Power-up Feature
o IEEE 1284 Parallel Port
- Standard mode -- Bi-directional SPP compliant
- Enhanced mode -- EPP V. 1.7 and 1.9 compliant
- High speed mode -- ECP, IEEE 1284 compliant
- Backdrive current reduction
- Printer power-on damage reduction
− Supports POST (Power-On Self Test) Data Port
o Floppy Disk Controller
- Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy
disk drives
- Enhanced digital data separator
- 3-Mode drives supported
- Supports automatic write protection via software
o 48 General Purpose I/O Pins
- Input mode supports switch de-bounce
- SMI is routed through GPIOs
o Flash ROM Interface
- Up to 4M bits flash supported
o Single 24/48 MHz Clock Inputs
o Single +5V Power Supply
o 128-Pin PQFP
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
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*Western Digital...
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*ZyMOS...
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