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**82396SX Smart Cache 12/17/90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**SL6012 Memory Mapper for PC-AT (74LS612 compatible) <Jul87
***Info:
The SL6012 Memory Mapper is intended for use in PC-AT design. It can
expand an address bus by 4 bits. In PC-AT applications, 4 bits of the
source address are used to select 1 of 16, eight bit map
registers. These registers are normally programmed (through software)
with the starting address of each memory page. The register data is
output directly for use as the most significant bits of the expanded
address bus. The 8 bits from the SL6012 are used along with the unused
source address bits to form the expanded address bus.
As shown in Table 1 [see datasheet], the SL6012 has three modes of
operation; read, write and map. Data may be written into, or read from
the Memory Mapper when chip select CSN is low. The register select
inputs (RS0 through RS3) select one of the sixteen map registers. When
RWN is low, data is written into a register from the data bus. When
RWN is high data is output from a Memory Mapper register to the data
bus.
The map mode of operation is selected when chip select CSN is high. In
this mode, the register data selected by the map address inputs (MA0
through MA3) will be available on the map outputs (MO0 through
MO7). Note that the map registers are addressed by either the RS
inputs or the MA inputs depending upon the operating mode. When MEN
(Map Enable) is low the map outputs (MO0-MO7) are active. When MEN is
high, the map outputs are at high impedance.
***Versions:...
***Features:...
**SL9010 System Controller (80286/80386SX/DX, 16/20/25MHz) <oct88...
**SL9020 Data Controller <oct88...
**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
**Other:...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**950 LPC I/O <07/16/99
***Info:
The SIS950 is a LPC Interface based highly integrated Super I/O. The
SIS950 provides the most commonly used legacy Super I/O functionality
plus the latest Environment Control initiatives, such as Hardware
Monitor, Fan Speed Controller and SiS’s "SmartGuardian" function. The
device’s LPC interface complies with Intel "LPC Interface
Specification Rev. 1.0" (Sept. 29, 1997). The SIS950 meets the
"Microsoft PC98 & PC99 System Design Guide" requirements and is ACPI
compliant.
The SIS950 features the enhanced hardware monitor providing 3 thermal
inputs from remote thermistors, thermal diode or diode-connected
transistor (2N3904). The device also provides the SiS innovative
intelligent automatic Fan ON/OFF & speed control functions
(SmartGuardian) to reduce overall system noise and power consumption.
The SIS950 has integrated nine logical devices, featuring an
Environment Controller (controls three Fans). The Environment
Controller has temperature, voltage and Fan Speed monitors. One Fan
Speed Controller is responsible to control three fan speeds through
three 128 steps of Pulse Width Modulation (PWM) output pins and to
monitor three fan's tachometer inputs.
Other features include one high-performance 2.88MB floppy disk
controller, with digital data separator, supporting two 360K/ 720K/
1.2M/ 1.44M/ 2.88M floppy disk drives. One multi-mode high-performance
parallel port features the bi-directional Standard Parallel Port
(SPP), the Enhanced Parallel Port (EPP V. 1.7 and EPP V. 1.9 are
supported), and the IEEE 1284 compliant Extended Capabilities Port
(ECP). Two 16C550 standard compatible enhanced UARTs perform
asynchronous communication, and support IR, one consumer remote
control (TV remote) IR, one MPU-401 UART mode compatible MIDI port,
one game port with built-in 558 quad timers and buffer chips to
support direct connection of 2 joysticks, and six ports (48 GPIO
pins). There is also a flash ROM interface with Address (FA[0:18]),
Data (FD[0:7]), and supporting three control signals FCS#, FWE# and
FRD#. In addition, a SmartGuardian engine is provided to monitor the
system condition and reacts to the detected condition accordingly.
These nine logical devices can be individually enabled or disabled via
software configuration registers. The SIS950 utilizes power-efficient
circuitry to reduce power consumption. Once a logical device is
disabled, the inputs are gated inhibit, the outputs are TRI-STATE and
the input clock is disabled. The SIS950 requires a single 48/24 MHz
clock input and operates with a single +5V power supply.
The SIS950 is available in 128-pin PQFP (Plastic Quad Flat Package).
***Versions:...
***Features:...
**Other:...
**PII/III/Pro...
**Athlon etc...
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