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*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
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*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810         (Whitney)       04/26/99...
***810L        (Whitney)       04/26/99...
***810-DC100   (Whitney)       04/26/99...
***810e        (Whitney)       09/27/99...
***810e2       (Whitney)       01/03/01...
***815         (Solano)        06/19/00...
***815e        (Solano-2)      06/19/00...
***815em       (Solano-?)      10/23/00...
***815ep       (Solano-3)      c:Nov'00...
***815p        (Solano-3)      c:Mar'01...
***815g        (Solano-3)      c:Sep'01...
***815eg       (Solano-3)      c:Sep'01...
***820         (Camino)        11/15/99...
***820e        (Camino-2)      06/05/00...
***830M        (Almador)       07/30/01...
***830MP       (Almador)       07/30/01...
***830MG       (Almador)       07/30/01...
***840         (Carmel)        10/25/99...
***845         (Brookdale)     09/10/01...
***845MP       (Brookdale-M)   03/04/02...
***845MZ       (Brookdale-M)   03/04/02...
***845E        (Brookdale-E)   05/20/02...
***845G        (Brookdale-G)   05/20/02...
***845GL       (Brookdale-GL)  05/20/02...
***845GE       (Brookdale-GE)  10/07/02...
***845PE       (Brookdale-PE)  10/07/02...
***845GV       (Brookdale-GV)  10/07/02...
***848P        (Breeds Hill)   c:Aug'03...
***850         (Tehama)        11/20/00...
***850E        (Tehama-E)      05/06/02...
***852GM       (Montara-GM)    01/14/03...
***852GMV      (Montara-GM)    ???...
***852PM       (Montara-GM)    06/11/03...
***852GME      (Montara-GM)    06/11/03...
***854         (?)             04/11/05...
***855GM       (Montara-GM)    03/12/03...
***855GME      (Montara-GM)    03/12/03...
***855PM       (Odem)          03/12/03...
***860         (Colusa)        05/21/01...
***865G        (Springdale)    05/21/03...
***865PE       (Springdale-PE) 05/21/03...
***865P        (Springdale-P)  05/21/03...
***865GV       (Springdale-GV) c:Sep'03...
***875P        (Canterwood)    04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C546/547     Python PTM3V                                     c:94
***Notes:...
***Info:
The  OPTi Python  Chipset provides  a highly  integrated  solution for
fully  compatible, high-performance  PC/AT  platforms. Together,  with
OPTi's  82C206 Integrated  Peripheral Controller  (IPC),  this chipset
will  support the  Pentium processor  in the  most cost  effective and
feature-rich designs available  today. This highly integrated approach
provides  the  foundation  for   a  cost  effective  platform  without
compromising performance. The OPTi  Python Chipset supplies a powerful
solution  positioned  to  deliver  value without  neglecting  quality,
compatibility, or reliability.

The  Python Chipset  is  comprised  of two  chips,  the 82C547  System
Controller (SYSC) and  the 82C546 AT Bus Controller  (ATC). A complete
Pentium  processor solution  consists of  the Python  Chipset  and the
82C206 Integrated Peripheral Controller (IPC).

82C546 (ATC) AT Bus Controller
The 82C546  ATC integrates the AT  bus interface and  data buffers for
transfers between the  CPU data bus, local data bus  and the DRAM data
bus. It also provides the ISA to local bus command translation.

o 208-pin PQFP
o Data bus buffer (host data to memory data)
o Data bus buffer control (ISA to memory)
o Parity generation and detection circuitry
o Keyboard controller chip select
o Local bus interface (ISA to local bus command translation)

82C547 (SYSC) System Controller
The  82C547 SYSC  provides  the  control functions  for  the host  CPU
interface, the  32-bit local  bus interface, the  64-bit Level  2 (12)
cache and  the 64-bit DRAM bus.  The SYSC also controls  the data flow
between the CPU bus, the DRAM bus, the local bus, and the 8/16-bit ISA
bus.

o 160-pin PQFP
o Pentium CPU interface
o DRAM controller
o L2 cache controller
o Ll cache controller
o Local bus interface
o Reset generation
o Arbitration logic
o Data bus buffer control (memory data to/from host data)
o Extended DMA page register
o Keyboard emulation of A20M# and CPU warm reset
o Port B and Port 92h Register

82C206 (IPC) Integrated Peripherals Controller
The 82C206  IPC provides two  DMA controllers, two  interrupt control-
lers, one timer/counter, and a real-time clock in an industry standard
single-chip  solution  for  the  peripherals  attached  to  the  PC/AT
peripheral bus.

o 84-pin PLCC or 100-pin PQFP
o Supports four DMA transfer modes
o Special Commands provided for ease of programming

Support Chips
The  82C606A and 82C606B  are two  buffer/translation devices  used to
translate  3.3V signals to  5.0V signal  levels in  Python motherboard
solutions. These devices buffer the CPU  address bus to the ISA and VL
address buses, the  82C546 ATC's memory data bus to  the ISA data bus,
the peripheral  XD bus  to the ISA  SA and  SD buses. The  82C606A and
82C606B integrate  a number of  glue logic TTL  devices (approximately
eleven), hence  reducing the  amount of TTL  on the  motherboard.  The
82C606A  and 82C606B  devices are  actually the  same device  with two
strapping options. Pulling the CONFI/2#  pin high causes the device to
function in the 82C606A Mode.  Pulling the CONFII2# pin low configures
the device to function in the 82C606B Mode of operation.

o 100-pin PQFP
o Mixed voltage to support 3.3V to 5.0V signal translation
o Two devices replace approximately eleven TTL devices

***Configurations:...
***Features:...
**82C556/7/8     Viper [no datasheet]                                ?...
**82C556/7/8N    Viper-N  Viper Notebook Chipset             <05/25/95...
**82C556M/7M/8E  Viper-N+ Viper Notebook Chipset                  c:96...
**82C566/7/8     Viper-Max Chipset Scalable MultiMedia PC Solution   ?...
**82C571/572     486/Pentium                                      c:93...
**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:
The P5  A.G.P./VGA chipset, SiS530/5595, provides  a high performance/
cost index  Desktop/Mobile solution  for the Intel  Pentium P54C/P55C,
AMD K5/K6/K6-II, Cyrix M1/M2 and  other compatible Pentium CPU with 3D
A.G.P. VGA system.

The Host,  PCI, 3D A.G.P.  Video/Graphics & Memory  Controller, SiS530
integrates the  Host- to-PCI bridge,  the PCI interface, the  L2 cache
controller, the  DRAM controller, the high  performance hardware 2D/3D
VGA controller, and the PCI IDE controller.

The   Host  interface   supports   Synchronous/Asynchronous  Host/DRAM
clocking configuration to eminently improve the system performance and
DRAM compatibility issues.

The L2 cache controller can support up to 2 MB P.B. SRAM, and the DRAM
controller  can support  SDRAM  memory  up to  1.5  GBytes with  three
double-sided  SDRAM  DIMMs  configuration.  The cacheable  DRAM  sizes
support up to 256 MBytes.

The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the
Ultra DMA33/66 function  that support the data transfer  rate up to 66
MB/s. It provides the separate data path for two IDE channels that can
eminently improve the performance under the multi-tasking environment.

The A.G.P. internal  interface is supported for integrated  H/W 3D VGA
controller. The  integrated VGA controller  is a high  performance and
targeted at  3D graphics application.  In addition,  the integrated 3D
Video/Graphics controller adopts the  64bits 100MHz host bus interface
high  technology  to  improve  the performance  eminently.   To  cost-
effective the PC system, the  share system memory architecture will be
adopted and  it can flexibly using  the 2MB, 4MB and  8MB frame buffer
size  from programming  the system  BIOS. [something  got  confused in
translation  there  didn't it?]  To  enhance  the system  performance,
SiS530 also supports the local  frame buffer solution and memory sizes
can support up to 8MB with SDRAM and SGRAM.

In addition  to provide  the standard interface  for CRT  monitors, it
also  provides  the Digital  Flat  Panel  Port  (DFP) for  a  standard
interface  between  a  personal  computer  and a  digital  flat  panel
monitor. This  port allows a host  computer to connect  directly to an
external  flat panel  monitor without  the need  for analog-to-digital
conversion  found  in most  flat  panel  monitors  today. As  for  DVD
solution,  the  integrated 3D  VGA  controller  also  support DVD  H/W
accelerator to improve the DVD playback performance.

The SiS5595 PCI  system I/O integrates the PCI-to-ISA  bridge with the
DDMA, PC/PCI DMA  and Serial IRQ capability, the  ACPI/Legacy PMU, the
Data  Acquisition   Interface,  the  Universal   Serial  Bus  host/hub
interface,  and the  ISA  bus  interface which  contains  the ISA  bus
controller, the DMA controllers, the interrupt controllers, the Timers
and  the  Real Time  Clock  (RTC).  It  also integrates  the  Keyboard
Controller and PS/2 mouse interface that can support keyboard power on
function  for users  to power  on system  by entering  the hot  key or
password from  keyboard. The built-in  USB controller, which  is fully
compliant to  OHCI (Open Host Controller Interface),  provides two USB
ports  capable  of  running  full/low  speed USB  devices.   The  Data
Acquisition Interface  offers the ability of  monitoring and reporting
the environmental  condition of  the PC. It  could monitor  5 positive
analog voltage inputs, 2 Fan speed inputs, and one temperature input.

In  addition, SiS5595  also supports  ACPI function  to  meet Advanced
Configuration and Power Interface (ACPI) 1.0 specification for Windows
98 environment,  it can support power-management  timer, Power button,
Real-time  clock alarm  wake up,  more  sleeping state,  ACPI LED  for
sleeping and  working state, LAN wake  up, Modem Ring In  wake up, and
OnNow initiative function.

***Configurations:...
***Features:...
**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...

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