[Home] [This version is outdated, a new version is here]
*Title...
*Search:...
*Read Me/FAQ/General Info...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:
The 50 MHz Intel486 DX  CPU-Cache Chip Set provides a high performance
solution  for  servers  and  high-end desktop  systems.   This  binary
compatible solution  has been optimized  to provide 50 MHz,  zero wait
state performance. The CPU-Cache chip set combines the 50 MHz Intel486
Microprocessor with  the 82495DX/82490DX cache  subsystem. It delivers
integer  performance of  41 V1.1  Dhrystone  MlPs and  a SPEC  integer
rating  of  27.9.  The  cache  subsystem  features  the 82495DX  Cache
Controller and the 82490DX Dual  Ported Data RAM.  Dual ported buffers
and registers  of the  82490DX allow the  82495DX Cache  Controller to
concurrently handle CPU bus, memory bus, and internal cache operations
for maximum performance.

The CPU-Cache Chip Set offers  many features that are ideal for multi-
processor  based systems.  The  Write-Back feature  provides efficient
memory  bus utilization  by reducing  bus traffic  through eliminating
unnecessary  writes  to main  memory.   The  CPU-Cache  chip set  also
supports MESI protocol and monitors  the memory bus to guarantee cache
coherency.

The 50  MHz Intel486  DX CPU and  82495DX/82490DX Cache  subsystem are
produced on  Intel's latest CHMOS  V process which  features submicron
technology and triple layer metal.

3.0 ARCHITECTURAL OVERVIEW
3.1 Introduction
The Intel486 CPU-cache chip  set provides a tightly coupled processing
engine  based on  the Intel486  microprocessor and  a  cache subsystem
comprised of  the 82495DX cache controller and  multiple 82490DX cache
components.   Figure 3.1  [see datasheet]  diagrams the  basic config-
uration.

The cache subsystem provides a  gateway between the CPU and the memory
bus. All CPU accesses that  can be serviced locally are transparent to
the memory bus and serve to avoid bus traffic.  As a result, the cache
chip  set  reduces memory  bus  bandwidth  to  both increase  Intel486
processor  performance and  support efficient  multiprocessor systems.
The  cache subsystem also  decouples the  CPU from  the memory  bus to
provide  zero-wait-state  operation at  high  clock frequencies  while
allowing relatively slow and inexpensive memories.

The  CPU-cache chip  set  prevents latency  and bandwidth  bottlenecks
across  a variety  of  uniprocessor and  multiprocessor designs.   The
processor’s  on-chip cache  supports  a  very wide  CPU  data bus  and
high-speed data  movement. The second-level cache  greatly extends the
capabilities of the on-chip cache resources, enabling a larger portion
of memory cycles to be satisfied independently of the memory bus.

3.2 CPU-Cache Chip Set Description
The chip set is comprised of three functional blocks: 

3.2.1 CPU
The chip  set includes a  special version of the  Intel486DX micropro-
cessor at  50 MHz.  The Intel486DX Microprocessor  Data Sheet provides
complete component specifications.

3.2.2 CACHE CONTROLLER
The 82495DX cache controller is  the main control element for the chip
set. providing  tags and line  states. and determining cache  hits and
misses. The 82495DX executes all  CPU bus requests and coordinates all
main memory accesses with the memory bus controller (MBC).

The 82495DX  controls the data  paths of the 82490DX  cache components
for cache hits and misses and furnishes the CPU with needed data.  The
controller  dynamically adds  wait  states as  needed  using the  most
recently used (MRU) prediction algorithm.

The 82495DX also performs memory bus snoop operations in shared memory
systems  and drives  the  cycle address  and  other attributes  during
memory bus accesses. Figure  3.2 [see datasheet] diagrams the 82495DX.

3.2.3 CACHE SRAM

Multiple  82490DX cache  components provide  the cache  SRAM  and data
path. Each component  includes the latches, muxes and  logic needed to
work in lock  step with the 82495DX to efficiently  serve both hit and
miss  accesses.  The 82490DX  components take  full advantage  of VLSI
silicon   flexibility   to  exceed   the   capabilities  of   discrete
implementations.  The  82490DX components support  zero-wait-state hit
accesses  and  concurrent  CPU  and  memory  bus  accesses,  and  they
replicate MRU  bits for autonomous  way prediction. During  memory bus
cycles. the 82490DX components act as a gateway between CPU and memory
buses. Figure 3.3 [see datasheet] diagrams an 82490DX cache component.

3.3 Secondary Cache Features

The 82495DX  cache controller and  82490DX cache components  provide a
unified, software  transparent secondary  data and  instruction cache.
The cache enables  a highspeed processor core  that provides efficient
performance even when paired with a significantly slower memory bus.

The secondary  cache interprets  CPU bus cycles  and can  service most
memory read and  write cycles without accessing main  memory.  I/O and
other special cycles are passed directly to the memory bus.  The cache
has a dual-port  structure that permits concurrent CPU  and memory bus
operation.

The 82495DX  cache controller  contains the 8K  tag entries  and logic
needed to support a cache as  large as 256K. Combinations of between 4
and 9 82490DX cache SRAMs are  used to create caches ranging from 128K
to 256K, with or without data parity.

The  MBC provides  logic  needed  to interface  the  CPU, 82495DX  and
82490DX  to the  memory  bus.   Because the  MBC  also affects  system
performance.  its design can be the basis of product differentiation.

***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
**530/5595       (Sinbad) Host, PCI, 3D Graphics & Mem. Ctrl.<11/10/98
***Info:...
***Configurations:...
***Features:
o   Supports Intel/AMD/Cyrix/IDT Pentium CPU Host Bus at 
    66/75/83/95/100 MHz and 2.5/3.3V Bus Interface
    − Supports the Pipelined Address of Pentium compatible CPU
    − Supports the Linear Address Mode of Cyrix CPU
    − 100/100, 95/95, 83/83, 75/75 and 66/66 MHz Synchronous 
      Host/DRAM clocking configuration
    − 100/75, 95/75, 83/66, 66/100 and 66/83 MHz Asynchronous 
      Host/DRAM clocking configuration
    − Supports Host Bus operation for integrated 3D VGA Controller
o   Meets PC99 Requirements
o   Supports PCI Revision 2.2 Specification
o   Integrated Super AGP VGA for Hardware 2D/3D Video/Graphics 
    Accelerators
    − Supports tightly coupled 64 bits 100MHz host interface to VGA 
      to speed up GUI performance and the video playback frame rate
    − Built-in programmable 24-bit true-color RAMDAC up to 230 MHz 
      pixel clock
    − Built-in reference voltage generator and monitor sense circuit
    − Supports loadable RAMDAC for gamma correction in high color 
      and true color modes
    − Built-in dual-clock generator
    − Supports Multiple Adapters and Multiple Monitors
    − Built-in PCI multimedia interface
    − Flexible design for shared frame buffer or local frame buffer 
      architecture
    − Shared System Memory Area 2MB, 4MB and 8MB
    − Supports SDRAM and SGRAM local frame buffer and memory size up 
      to 8 MB
    − Supports Digital Flat Panel Port for Digital Monitor (LCD Panel)
    − Supports DVD H/W Accelerator
o   Integrated Second Level ( L2 ) Cache Controller
    − Write Back Cache Mode
    − Direct Mapped Cache Organization
    − Supports Pipelined Burst SRAM
    − Supports 256K/512K/1M/2M Bytes Cache Sizes
    − Cache Hit Read/Write Cycle of 3-1-1-1
    − Cache Back-to-Back Read Cycle of 3-1-1-1-1-1-1-1
    − Supports Single Read Allocation for L2 Cache
    − Supports Concurrency of CPU to L2 cache and Integrated A.G.P. 
      VGA master to DRAM accesses
o   Integrated DRAM Controller
    − Supports up to 3 double sided DIMMs (6 rows memory)
    − Supports 8Mbytes to 1.5 GBytes of main memory
    − Supports Cacheable DRAM Sizes up to 256 MBytes
    − Supports 1M/2M/4M/8M/16M/32M x N for 2-bank or 4-bank SDRAM
    − Supports 3.3V DRAM
    − Supports Concurrent Write Back
    − Supports CAS before RAS Refresh, Self Refresh
    − Supports Relocation of System Management Memory
    − Programmable CS#, DQM#, SRAS#, SCAS#, RAMWE# and MA Driving 
      Current
    − Option to Disable Local Memory in Non-cacheable Regions
    − Entries GART cache to Minimize the Number of Memory Bus Cycles 
      Required for Accessing Graphical Texture Memory
    − Programmable Counters to Ensure Guaranteed Minimum Access Time 
      for Integrated A.G.P. VGA, CPU, and PCI accesses
    − Two Programmable Non-cacheable Regions
    − Supports X-1-1-1/X-2-2-2 Burst Write Cycles
    − Fully Configurable for the Characteristic of Shadow RAM (640 
      KBytes to 1 MBytes)
    − Shadow RAM in Increments of 16 KBytes Built-in 8 Way 
      Associative/16
    − Supports SDRAM 7/8-1-1-1 Burst Read Cycles
o   Provides High Performance PCI Arbiter
    − Supports up to 4 PCI Masters
    − Supports Rotating Priority Mechanism
    - Hidden Arbitration Scheme Minimizes Arbitration Overhead
    - Supports Concurrency between CPU to Memory and PCI to PCI
    - Supports Concurrency between CPU to 33Mhz PCI Access and 33Mhz 
      PCI to integrated A.G.P. VGA Access
    - Programmable Timers Ensure Guaranteed Minimum Access Time for 
      PCI Bus Masters, and CPU
o   PCI Bus Interface
    - Supports 32-bit PCI local bus standard Revision 2.2 compliant
    - Integrated write-once subsystem vendor ID configuration register
    - Supports zero wait-state memory mapped I/O burst write
    - Integrated 2 stages PCI post-write buffer to enhance frame 
      buffer write performance
    - Integrated 256 bits read cache to enhance frame buffer read 
      performance
    - Supports full 16-bit re-locatable VGA I/O address decoding
o   Integrated Host-to-PCI Bridge
    - Supports Asynchronous PCI Clock
    - Translates the CPU Cycles into the PCI Bus Cycles
    - Zero Wait State Burst Cycles
    - Supports Pipelined Process in CPU-to-PCI Access
    - Maximum PCI Burst Transfer from 256 Bytes to 4 Kbytes
    - Supports Memory Remapping Function for PCI master accessing 
      Graphical Window
o   Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
    - Supports Graphic Window Size from 4MBytes to 256MBytes
    - Supports Pipelined Process in CPU-to-Integrated 3D A.G.P. 
      VGA Access
    - Supports 8 Way, 16 Entries Page Table Cache for GART to enhance 
      Integrated A.G.P. VGA Controller Read/Write Performance
    - Supports PCI-to-PCI bridge function for memory write from 33Mhz 
      PCI bus to Integrated A.G.P. VGA
o   Integrated Posted Write Buffers and Read Prefetch Buffers to 
    Increase System Performance
    - CPU-to-Memory Posted Write Buffer (CTMFF) with 12QW Deep, Always 
      Sustains 0 Wait Performance on CPU-to-Memory
    - CPU-to-Memory Read Buffer with 4 QW Deep
    - CPU-to-PCI Posted Write Buffer with 2 QW Deep
    - PCI-to-Memory Posted Write Buffer with 8 QW Deep, Always 
      Streams 0 Wait Performance on PCI-to/from-Memory Access
    - PCI-to-Memory Read Prefetch Buffer with 8 QW Deep
    - CPU-to-VGA Posted Write Buffer with 4 QW Deep
o   Fast PCI IDE Master/Slave Controller
    - Bus Master Programming Interface for Windows 98 Compliant 
      Controller
    - Plug and Play Compatible
    - Supports Scatter and Gather
    - Supports Dual Mode Operation - Native Mode and Compatibility 
      Mode
    - Supports IDE PIO Timing Mode 0, 1, 2 ,3 and 4
    - Supports Multiword DMA Mode 0, 1, 2
    - Supports Ultra DMA 33/66
    - Two Separate IDE Bus
    - Two 16 DW FIFO for PCI Burst Transfers.
o   Supports NAND Tree for Ball Connectivity Testing
o   576-Balls BGA Package
o   3.3V Core with mixed 2.5V, 3.3V and 5V I/O CMOS Technology

**540            (Spartan) Super7 2D/3D Ultra-AGP Single C.S.<11/30/99...
**55x            SoC (System-on-chip)                        <03/14/02...
**
**Support chips:
**85C206     Integrated Peripheral Controller [no datasheet]         ?...
**5595       Pentium PCI System I/O                          <12/24/97...
**950        LPC I/O                                         <07/16/99...
**Other:...
**PII/III/Pro...
**Athlon etc...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...