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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*OPTi...
**82C898         System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:
Overview
The 82C898 provides a highly integrated solution for fully compatible,
high performance PC/AT platforms. The 82C898 supports 486SX/DX/DX2/DX4
and  P24T  microprocessors  in  the  most  cost  effective  and  power
efficient designs  available today. For  high-end system applications,
this  device offers  optimum  performance for  systems  running up  to
50MHz.  

Based  fundamentally  on  OPTi’s   proven  82C801  and  82C802  design
architectures,  the 82C898 adds  additional memory  configurations and
extensive  power  management  control  for  the  processor  and  other
motherboard components.

The 82C898  supports the latest  in write-back processor  designs from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus  for compatibility  and performance.  It also  includes  an 82C206
Integrated Peripherals Controller (IPC),  all in a single 208-pin PQFP
(Plastic Quad Flat Pack) for low cost.

Power Management
Figure  2-1   [see  datasheet]  exemplifies  the   flexibility  of  an
82C898/82C602-based designs GREEN strategy.  System designs can easily
accommodate both  SLe and non-SLe  CPUs.  If  an Intel non-SLe  CPU is
used, SMI#, SMIAOT#, and FLUSH# are no connects. One design can easily
accommodate  both  types  of   processors  with  minimal  changes  for
upgrades.

***Configurations:...
***Features:...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94
***Notes:...
***Info:
OPTi's  82C822 VESA  local bus  to PCI  Bridge (PCIB)  chip is  a high
integration  208-pin PQFP  device designed  to work  with VESA  VL bus
compatible core logic chipsets.  The 82C822 PCIB provides interface to
the high performance PCI bus and is fully compliant to the PCI Version
2.0 specification. The 82C822 requires  no glue logic to implement the
PCI  bus interface  and hence  it allows  designers to  have  a highly
integrated  motherboard with  both VESA  local bus  and PCI  local bus
support. The PCIB chip  offers premium performance and flexibility for
VESA VL-based desktop systems running up to 50MHz. The 82C822 PCIB can
be used with  OPTi's 82C802G core logic and  82C602 buffer chipsets to
build a  low cost and  power efficient 486-based desktop  solution. It
also works  with OPTi 82C546/547  chipset to build a  high performance
PCI/VL solution based on the Intel P54C processor.

The 82C822 PCIB provides all of the control, address and data paths to
access  the PCI  bus from  the  VESA Local  bus (VL  bus). The  82C822
provides  a  complete  solution  including data  buffering,  latching,
steering, arbitration, DMA and  master functions between the 32-bit VL
bus and the 32-bit PCI bus.

The PCIB works seamlessly with  the motherboard chipset bus arbiter to
handle all requests of the host  CPU and PCI bus masters, DMA masters,
I/O relocation  and refresh. Extensive register and  timer support are
designed into the 82C822 to implement the PCI specification.

The 82C822 is a  true VESA to PCI bridge. It  has the highest priority
on  CPU accesses  after cache  and system  memory. It  generates LDEV#
automatically  and  then  compares  the addresses  with  its  internal
registers to determine whether the current  cycle is a PCI cycle. When
a cycle  is identified  as PCI  cycle, the 82C822  will take  over the
cycle and then return RDY# to the CPU. If not, the 82C822 will give up
the  cycle to  the local  device  or, in  the  case of  an ISA  slave,
generate a  BOFF# cycle to the  CPU. This action will  abort the cycle
and allow the CPU to rerun the cycle.

The 82C822 includes  registers to determine shadow  memory space, hole
locations  and sizes  to allow  the 82C822  to determine  which memory
space should be local and which is located on the ISA bus. Upon access
to memory, the 82C822 can determine whether  or not the cycle is a PCI
access by comparing the cycle with its internal registers.

***Versions:...
***Features:...
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