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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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*OPTi...
**82C898         System/Power Management Controller (non-cache)c:Nov94
***Notes:...
***Info:
Overview
The 82C898 provides a highly integrated solution for fully compatible,
high performance PC/AT platforms. The 82C898 supports 486SX/DX/DX2/DX4
and  P24T  microprocessors  in  the  most  cost  effective  and  power
efficient designs  available today. For  high-end system applications,
this  device offers  optimum  performance for  systems  running up  to
50MHz.  

Based  fundamentally  on  OPTi’s   proven  82C801  and  82C802  design
architectures,  the 82C898 adds  additional memory  configurations and
extensive  power  management  control  for  the  processor  and  other
motherboard components.

The 82C898  supports the latest  in write-back processor  designs from
Intel, AMD, and Cyrix, as well as supporting the AT bus and VESA local
bus  for compatibility  and performance.  It also  includes  an 82C206
Integrated Peripherals Controller (IPC),  all in a single 208-pin PQFP
(Plastic Quad Flat Pack) for low cost.

Power Management
Figure  2-1   [see  datasheet]  exemplifies  the   flexibility  of  an
82C898/82C602-based designs GREEN strategy.  System designs can easily
accommodate both  SLe and non-SLe  CPUs.  If  an Intel non-SLe  CPU is
used, SMI#, SMIAOT#, and FLUSH# are no connects. One design can easily
accommodate  both  types  of   processors  with  minimal  changes  for
upgrades.

***Configurations:...
***Features:...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
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