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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*Motorola...
*OPTi...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92
***Info:
The OPTi 82C497 is a Direct Mapped Write Back cache controller with
one level write buffer that is an optional part of the DXBB (Building
Block) Chip set. The DXBB also contains the 82C496 and the 82C206,
which form the heart of the system. The 82C497 is added to the DXBB
chip set for cache based systems.
The OPTi 82C496 offers an upgradable CPU module base-board solution
for the 80386 or the 80486 PC/AT system. By swapping the CPU module,
the vendor can configure the 82C496 driven base-board into various
32-bit AT systems - 386 or 486 CPU, with cache or without cache and
rated at 16MHz- 50MHz.
For the Non-Cache systems, the CPU interfaces directly with the 82C496
and the local devices, like the local VGA controller or the local hard
disk adaptor.
For cache based systems the 82C497 (the cache controller) sits between
the CPU and the 82C496 and the local devices. All the high frequency
signals are isolated by the 82C497. This allows the base-board to run
at a fixed speed (25 or 33MHz) - while the CPU and the Cache can run
synchronously at any determined rated speed. This provides a reliable
upgrade method for the CPU modules.
***Configurations:...
***Features:...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94
***Notes:...
***Info:...
***Configurations:...
***Features:
o Processor interface:
- Intel 80486SX, DX, DX2, SLe, DX4, P24T, P24D
- AMD 486DX, DX2, DXL, DXL2, Plus
- Cyrix DX, DX2, M7
- CPU frequencies supported 20, 25, 33, 40 and 50MHz
o Cache interface:
- Direct Mapped Cache
- Two banks interleaved or single bank non-interleaved
- 64, 128, 256 and 512K cache sizes
- Programmable wait states for L2 cache reads and writes
- 2-1-1-1 read burst and zero wait state write @ 33MHz
- No Valid bit required
- Supports CPUs with L1 write-back support
o DRAM interface:
- Up to 128MB main memory support
- Supports 256KB, 1MB, 4MB, and 16MB single- and double-sided SIMM
modules
- Read page-hit timing of 3-2-2-2 at 33MHz
- Supports hidden, slow and CAS-before-RAS refresh
- Four RAS lines to support four banks of DRAM
- Programmable wait states for DRAM reads and writes
- Enhanced DRAM configuration map
o Power management:
- Support for SMM (System Management Mode) for system power
management implementations
- Programmable power management
- Programmable wake-up events through hardware, software and
external SMI source
- Multiple level GREEN support (NESTED_GREEN)
- STPCLK# protocol support
- One programmable GREEN event timer
o ISA interface:
- 100% IBM PC/AT ISA compatible
- Integrates DMA, timer and interrupt controllers
- Optional PS/2 style IRQ1 and 12 latching
o VESA VL interface:
- Conforms to the VESA v2.0 specification
- Optional support for up to two VL masters
o Miscellaneous features:
- Full support for shadow RAM, write protection, L1/L2
cacheability for video, adapter and system BIOS
- Enhanced arbitration scheme
- Transparent 8042 emulation for fast CPU reset and GATEA20
generation
o Packaging:
- Higher integration
- Reduced TTL count
- Low-power, high-speed 0.8-micron CMOS technology
- 208-pin PQFP (Plastic Quad Flat Pack)
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
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*Western Digital...
*Winbond...
*ZyMOS...
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