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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91
***Info:
The HT22  is an  advanced PC/AT compatible,  single-chip 80386SX/80286
system  design solution.   This highly  integrated single  chip allows
simple, low  cost system design  options while featuring  high perfor-
mance,  low  power  consumption,  and  minimum  board  space  require-
ments. Advanced  memory management  features include support  for page
mode,  2 or  4-way interleaving  in both  pipelined  and non-pipelined
modes.  The EMS  4.0 hardware implementation features dual  sets of 32
registers   with  full   context  support   for   highest  performance
optimization  of  extended local  memory  accesses.   An advanced  EMS
hardware  write-protect option  has  been added  for  maximum EMS  4.0
compatibility. The HTZ2 supports 256K, 1M  and 4MB DRAMs in 1 by 1 and
1 by 4 device configurations for up to 20MB of on-board system memory.
16MB  is  addressed  directly   by  system  resources,  the  remainder
addressed by the EMS mode.

A flexible Shadow  RAM option for System and Video BIOS  as well as 8-
16-bit BIOS options adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT22 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC  core logic requirements. The chip  also contains all
the  necessary  address buffers,  data  transceivers, memory  drivers,
parity  checking   and  supporting  circuitry  for   a  complete  high
performance computer  solution.  An  asynchronous AT Bus  clock allows
for  a constant 8MHz  Bus clock  rate for  highest bus  device compat-
ibility as  defined in IEEE  Spec P996. This  device is packaged  in a
208-pin Plastic Quad Flat Pack.

***Configurations:...
***Features:...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C571/572     486/Pentium                                      c:93
***Notes:...
***Info:...
***Configurations:...
***Features:
o   100% PC/AT compatible 
o   Fully supports the Intel 486 and Pentium microprocessor 
o   Three chip PC/AT solution: 82C571, 82C572 and 82C206 
o   IX clock source, supporting systems running up to 66 MHz 
o   Write Back, direct-mapped cache with size selections: 
    64K, 128K, 256K, 512K, 1Mb 
o   Programmable cache write policy: write-back or write through 
o   Fully programmable cache and DRAM read/write cycles 
o   Supports 3-2-2-2 cache burst read cycle at 66 MHz 
o   Built-in TAG auto-invalidation circuitry 
o   Support for two programmable non-cacheable/system memory "hole" 
    regions 
o   Supports two banks of 64-bit wide DRAMs with 
    256K, 512K, 1 M, 2M, 4M, and 8M x 36 page-mode DRAMs 
o   Supports DRAM burst cycles 
o   DRAM post write buffer 
o   Provides Flash ROM support 
o   33 MHz asynchronous 32-bit VESA VL Local Bus support 
o   Performance oriented snoop-line comparator for VL/ISA bus 
    masters 
o   Extended DMA page register 
o   Asynchronous CPU and VL bus interface 
o   AT bus clock speed programmability 
o   Low power, high speed CMOS technology 

**82C576/7/8     Viper Xpress  [no datasheet]                        ?...
**82C576/8/9     Viper XPress+ [no datasheet, some info]     <01/16/97...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...