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**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:...
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96
***Notes:...
***Info:...
***Configurations:...
***Features:
System
o 100% PC/AT compatible
o Supports 3.3V Intel Pentium 75/90/100/120 processors at bus
frequencies up to 66MHz
o Supports Cyrix 6x86 processor
DRAM
o Full 64-bit FPM/EDO DRAM controller
- Supports 2-2-2 EDO pipeline at 66MHz bus speed
- Supports 5V or 3.3V DRAM with-out buffers
- Supports up to 512MB
- Controls up to 6 banks
- Post write buffer
o Selectable current drive for DRAM bus
Cache
o L1 Cache supports write-through and write-back modes
o Power managed L2 Cache
- 64KB-2MB cache
- Write-back or write-through modes
- 2-1-1-1 synchronous cache cycles
- 3-1-1-1 pipelined synchronous cache cycles
- Combined tag/dirty SRAM option
ISA/VL/PCI Bus
o Integrated PCI bus with operation up to 33MHz; supports up to
three masters
o CLKRUN# support for PCI
o Distributed DMA support (software-based)
o 100% AT-compatible ISA bus; 3.3V or 5V operation, also supports
ISA bus masters
o VL bus support (slave only)
o Integrated Local Bus IDE supports four drives, which can be bus
masters, modes 4 and 5 supported
Power Management
o Advanced Power Management Unit
o Full CPU System Management Mode (SMM) support
o Full CPU power control through "clock throttling"
o Full system clock control, even CPU clock can be stopped during
APM doze mode
o Both hardware and software controlled power management
o Full peripheral power control
o 13 flexible peripheral timers
o Sixteen power control pins
o I/O trapping captures address and data
o Distributed DMA support (software-based)
o Full peripheral activity tracking
o Automatic peripheral power-up/power-down features
o Full suspend current leakage control
o 36 Power Management Interrupt (PMI) sources
o Eight external power management interrupt sources
o Supports SMBASE re-programmability that allows the cache to be
maintained during system management mode, avoiding cache fills
after returning from SMM
o Proprietary automatic internal pull-up/pull-down resistors
activated only when needed to reduce power consumption
Thermal Management
o Advanced Thermal Management Unit
o Internal mechanism tracks CPU activity and initiates cool down
mode before CPU temperature reaches a damaging level
o External sensor option
Packaging
o 82C556M Data Buffer
- 176 pin TQFP (0.5mm pin spacing)
o 82C557M System Controller
- 208 pin TQFP (0.5mm pin spacing)
o 82C558E Peripheral Controller
- 208 pin TQFP (0.5mm pin spacing)
82C602A RTC/Buffer Companion Chip
o Integrated Real-Time Clock
o Based on Benchmark Bq3285
o 256 bytes battery-backed memory
o Integrates multiplexing/demultiplexing logic, latches, and
buffers
o Eliminates most/all TTL in typical synchronous cache system
o 100 pin TQFP package (0.5mm pin spacing)
o Also available in 100 pin PQFP
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?
***Info:
Overview
The OPTi Viper-MAX Chipset provides a highly integrated solution for
fully compatible, high performance PC/AT platforms based on the Intel
3.3V Pentium Processor, Cyrix 6x86 Processor, and AMD K86 Proc-
essor. As the latest member of the Desktop Viper Chipset Family, it is
designed from its inception to be the highest performance Pentium
chipset ever. its feature set can be scaled to address entry level
UMA-based system to high-end non-UMA work stations and servers. The
deep buffers in the Viper-MAX minimize system level latencies and
maximize through-puts to both DRAM and PCI subsystems.
The chipset provides 64-bit core logic, with Unified Memory Archit-
ecture (UMA), and integrated PCI support, plus sophisticated power
management features. This highly integrated approach supplies the
foundation for a cost effective platform without compromising per-
formance. Its feature set furnishes an array of control and status
monitoring options that are accessed through a simple and straight-
forward interface. All major BIOS vendors provide extensive software
hooks that allow system designers to integrate their own special
features with minimal effort.
82C566 Data Buffer Controller
The 82C566 performs the task of buffering the CPU to the DRAM memory
data path.
o CPU to memory data buffer
o CPU to PCI local bus buffer
o Memory to PCI local bus buffer
o 208-pin PQFP
82C567 System Controller
The 82C567 provides the control functions for the host CPU interface,
the 64-bit Level-2 (L2) cache, the 64-bit DRAM bus, and the PCI
interface. The 82C567 controls the data flow between the CPU bus, the
DRAM bus, the local buses, and the 8/16-bit ISA bus. It interprets and
translates cycles from the CPU, PCI bus master, ISA master, and DMA to
the host memory, PCI bus slave, or ISA bus devices. The 82C567 also
serves as the UMA (Unified Memory Architecture) and USB (Universal
Serial Bus) protocol interface.
o 3.3V CPU interface
o DRAM controller
o L1/L2 cache controller
o UMA arbiter
o USB interface
o PCI interface
o Arbitration logic
o Data bus buffer control (memory data bus to and from host data
bus)
o 208-pin PQFP
82C568 Integrated Peripherals Controller
The 820568 contains the ISA bus controller and includes an 82C206, RTC
interface, DMA controller, serial interrupt controller and distributed
DMA. It also has a sophisticated system power management unit.
o ISA bus controller
o Master mode IDE
o Type F DMA support
o Integrated 82C206 IPC
o System power management functions
o PCI local bus interface
o PCI to ISA expansion bridge
o Serial interrupt controller
o Distributed DMA
o Keyboard emulation of A20M# and CPU warm reset
o Port B and Port 092h Register
o 208-pin POFP
***Configurations:...
***Features:...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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