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**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92
***Info:...
***Configurations:...
***Features:
o 386 and 486 CPU interface
o Isolates the CPU bus from Local bus, more reliable system
operation at high speed
o Asynchronous handshaking between CPU bus and Local bus; fixed
base-board speed with upgradeable CPU card speed
o Direct map write back cache with one level write buffer and
16-byte line size
o Programmable 2-1-1-1, 3-1-1-1, 2-2-2-2 or 3-2-2-2 burst read cycle
o Programmable cache write hit 0 or 0 wait state
o Optional Dirty bit
o Supports 32K - 256K cache size for 386 cache system
o Supports 64K - 512K cache size for 486 cache system
o Provides TAG and Dirty RAM test capability
o Built-in TAG auto-invalidation circuitry
o Two programmable non-cacheable regions
o Option for write-protected, cacheable Video BIOS
o Cacheable AT bus memory space
o 8042 emulation for fast CPU-reset and gate A20 generation
o 1X clock source support for systems from 16 MHZ to 50 MHZ
o 160-pin plastic quad flat package
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95
***Notes:...
***Info:
The OPTi Viper (820556/557/558N) Notebook Chipset provides a highly
integrated solution for fully compatible, high performance PC/AT
platforms based on Intel's 3.3V Pentium Processor, Cyrix's M1 Proce-
ssor, and AMD's K5 Processor. The chipset provides 64-bit core logic,
integrated PCI and VL support, and Sophisticated power management
features. This highly integrated approach supplies the foundation for
a cost effective platform without compromising performance. Its feat-
ure set furnishes an array of control and status monitoring options
that are accessed through a simple and straightforward interface. All
major BIOS vendors provide extensive software hooks that allow system
designers to integrate their own special features with minimal effort.
The Viper Notebook Chipset is comprised of three chips:
o 82C556 Data Buffer Controller (DBC),
o 82C557 System Controller (SYSC),
o 82C558N Integrated Peripherals Controller (IPC)
82C556 Data Buffer Controller (BBC)
The 82C556 DBC performs the task of buffering the CPU to the DRAM
memory data path. It also performs parity checking.
o CPU to memory data buffer
o CPU to local bus buffer
o Memory to local bus buffer
o 176-pin TQFP or 160-pin PQFP
82C557 System Controller (SYSC)
The 82C557 SYSC provides the control functions for the host CPU
interface, the 64-bit Level-2 (L2) cache. the 64-bit DRAM bus. the VL
bus interface, and the PCI interface. The SYSC also controls the data
flow between the CPU bus, the DRAM bus, the local buses, and the
8/16-bit ISA bus. The SYSC interprets and translates cycles from the
CPU. PCI bus master. ISA master, and DMA to the host memory, local bus
slave, PCI bus slave, or ISA bus devices.
o 3.3V CPU interface
o DRAM controller
o L2 cache controller
o L1 cache controller
o PCI interface
o Arbitration logic
o Data bus buffer control (memory data bus to and from host data bus)
o VL bus interface
o 208-pin PQFP or TQFP
82C558N Integrated Peripherals Controller (IPC)
The 820558N Integrated Peripherals Controller (IPC) contains the ISA
bus controller and includes an 820206, RTC interface, DMA controller,
PCI arbitration logic. and a sophisticated system power management
unit. It also includes buffers and steering control for the 32-bit PCI
interface.
o ISA bus controller
o Integrated 82C206 IPC
o CPU thermal management functions
o System power management functions
o PCI local bus interface
o Keyboard emulation of A20M# and CPU warm reset
o Port B and Port 92h Register
o 208-pin PQFP or TQFP
***Configurations:...
***Features:...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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