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**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
**HTK320 386DX Chip Set c:Sep91
***Info:
The HTK320 chip set is a 2-chip, high-performance, cost-effective
solution for the 80386DX microprocessor. In its minimum configuration,
this highly integrated chip set requires only four external TTL
devices to implement a fully compatible IBM PC/AT system at speeds up
to 40 MHz.
The HTK320 is based on Headland’s Bus Architecture and consists of the
HT321-ISA Controller and the HT322-Memory Control Unit (MCU) packaged
in two 184-pin plastic quad flat packs. Among its features are an
on-chip cache controller and internal tag RAM.
Unlike other 3rd generation chip sets that have integral Cache
Controllers, the HTK320 integrates the high-speed tag RAM into the
chip set to enhance performance and significantly reduce component
count and manufacturing cost. The direct mapped or 2-way set
associative cache design supports external cache sizes of 32K, 64K,
and 128K.
The HTK320 can support Peripheral Devices such as VGA or SCSI
controllers on the local processor bus, or any 3rd party device that
is designed to work within the 386DX Bus Protocol and Timing. By
eliminating the ISA backplane bottleneck, system designers can greatly
improve the performance of functions such as graphics generation and
disk access.
The HTK320 incorporates a 4-leve1 deep Write Buffer and performs byte
gathering into 32 bit accesses to the DRAM. This facilitates real
zero wait state writes and, when coupled with the 2-way set
associative cache, provides enhanced memory performance.
The HTK320 Supports up to 4 banks of DRAM, configurable as 1-4 Banks.
This flexible memory architecture allows for any memory type, from
256Kb to 16Mb devices, in any bank. Maximum system performance is
achieved from the DRAM banks through various means, including
interleave of Memory Bank and/or Page, and CAS before RAS refresh.
The memory may also be tuned to its maximum potential through the use
of extensive DRAM timing Control Registers, controls include,
Precharge time, Access time on Reads, Active time on Writes, as well
as CAS and RAS delays. In addition, further system performance is
gained by separate timing parameters on the read and Write cycles
which allow system designers to take maximum advantage of the
pipelined structure of the chip set.
The HTK320 also supports extensive mapping registers, which allow
system designers to take maximum advantage of system memory. The chip
set supports EMS LIM 4.0, allows for mixed Shadow/Remap in 16K blocks
between the 640K and 1M boundaries, and eliminates the requirement fer
external decoding logic by support of 27 Programmable Non-cache
regions. With the' extensive HTK320 mapping capability, it is
feasible to seamlessly place 3rd party devices on the local bus
without the need for external TTL support. The HTK320 Mapping
structure provides for a single 8-bit EPROM to be used for both the
system and Video BIOS, further reducing the system chip count and
cost.
***Configurations:...
***Features:...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C281/282 Cache Sx/AT (386SX) <08/22/91
***Notes:...
***Info:
The 82C281/2 is a highly integrated AT system logic VLSI for high end
386 Sx AT systems. It integrates the logic for local DRAM control, AT
bus control, cache memory control, and data bus control and is
designed for systems running at 16MHz, 20MHz, and 25MHz.
A high performance, compact 386 Sx/AT system can be implemented easily
with 82C281/2 and standard peripheral controllers like the 82C206 or
the VLSI 82C100 plus Dallas Semiconductor DS1287.
2 System Operation
The following sections describe the detailed system operations of the
82C281 /2 based Sx-AT design.
2.1 Reset
The power good (PWRGD) signal from power supply drives the system into
the initial state when it is asserted low. The 82C281/2 forces CPURST,
SYSRST, and NPRST high as soon as PWRGD becomes inactive. When the
PWRGD is high, the chip deactivates the CPURST, SYSRST, and NPRST
after 128 CLK2 cycles.
2.2 Cache Interface
The 82028112 cache control unit monitors the HIT# pin and the internal
NCA# signals to determine if it is a cache hit or cache miss
cycle. During the cache read miss cycle, the cache controller asserts
TAGWE# to update the TAG RAM, CAWE# is also asserted to update the
cache data memory.
The A1 CNT output will be forced high then low to toggle CPU address
bit 1 to cache data memory to achieve the prefetch.
During cache write hit cycles, the cache controller asserts the CAWE#
signal to update the cache data memory.
2.3 Local DRAM Interfaces
Local DRAM is located on the CPU local data bus and is buffered by a
F244 and F373 buffer. During CPU read cycles data is routed from main
memory to CPU through F244’s Which are controled by LMRD#. During CPU
write cycles, data is latched by F373 latches with the PDLTH signal
from the 82C281/2 while DWE# controls the transceivers' enable. The
main memory subsystem asserts the LMRD# while CPU, DMA, and external
master card reads the local DRAM. DWE# is asserted during local DRAM
memory write.
For local memory read cycles, the memory controller reads two bytes at
a time. The read data passes into 82C281/2 where the parity checking
function is executed.
For the local memory write cycles, the data bus control unit generates
the parity bits to be stored into the local DRAM.
2.4 System BIOS ROM
If the system BIOS ROM is not shadowed, the ROM cycles are treated as
AT cycles. The system designer can put the ROM on the XD bus as an
8-bit slave or SD bus as a 16-Bit slave.
For a 16-bit slave, ROMCS# is connected to M16# through an open
collector driver such as a 7407, the 82C281/2 monitors M16# to
determine the width of the ROM data path.
2.5 I/O Ports located on the XD bus
For l/O ports located on the XD bus, the XDIR# is activated. I/O ports
0F0H - 0FFH are reserved for the coprocessor.
2.6 Refresh Cycles
The AT bus control unit arbitrates the hold request from 82C206 and
the refresh request from 82C281/2 internal, then decides which is the
next owner of the bus once the CPU relinquishes it. The refresh
request generated internally by 82C281/2 can be programmed as every
15.9 micro-seconds or every 95.5 micro-seconds for slow refresh
DRAM. lf the bus is granted for refresh cycles, the AT bus control
unit asserts RFSH# and MEMRD# commands and also generates the refresh
address.
2.7 DMA Cycles
The hold request from the 82C206 initiates DMA/Master transfers. The
82C281/2 performs the arbitration between HRQ and refresh
request. After the CPU acknowledges by asserting HLDA, and DMA request
wins the arbitration, the 82C281/2 sends HLDA1 to the 82C206
acknowledging the request. The 820206 then asserts DMA16# and
activates ADS16# to start 16-bit DMA transfers, or asserts DMA8# and
activates ADS8# to start 8-bit DMA transfers.
***Configurations:...
***Features:...
**82C283 386SX System Controller c:91...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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