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**M1489/87 FinALi-486 PCI Chipset <Feb95
***Info:
ALi's M1489/M1487 PCI chipset is the most cost effective PCI solution
available. M1489/M1487 enables top-to-bottom PCI in 486 CPU systems,
offering superior price/performance for mainstream PCI-ISA systems.
M1489/M1487 highly integrates the DRAM controller, L2 cache control-
ler, Host, PCI, and ISA interface, as well as the standard ISA
functions: DMA controller, interrupt controller, timer/counter, RTC
(Real Time Clock), and keyboard controller. Additionally, M1489/M1487
incorporates the high performance Local Bus IDE allowing a system de-
signer to implement Local bus IDE with no additional cost. M1489/M1487
is a highly integrated solution requiring minimized TTL components,
enabling PCI-ISA designs at costs equal to or lower than comparable VL
Bus designs.
M1489 (Cache Memory PCI Controller: CMP) integrates the L2 cache con-
troller and the DRAM controller. The cache controller supports
write-back cache policies and cache size from 128K to 1M byte in an
interleaved or non-interleaved configuration. The DRAM controller
interfaces DRAM to the Host bus, PCI bus, and Link bus. M1489 can
support EDO 3/5V DRAM, standard DRAM, and flexible timing
select. M1489 also integrates intelligent Host to PCI, PCI to Host
buffer to achieve high performance. Also, M1489 provides the high
performance Local Bus IDE interface.
M1487 (ISA Bridge Controller: IBC) provides the bridge between the ISA
bus, PCI bus, and Host bus. IBC integrates the common I/O functions
found in today's ISA based systems: a seven channel DMA, two 82C59
interrupt controllers, 8254 timer/ counter, deep green function, and
control logic for NMI generation. IBC also has built-in 128 bytes RTC,
MC14069, KBC, and 7406. IBC also provides the decode for external
BIOS.
***Configurations:...
***Features:...
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**800 series
***810 (Whitney) 04/26/99...
***810L (Whitney) 04/26/99...
***810-DC100 (Whitney) 04/26/99...
***810e (Whitney) 09/27/99...
***810e2 (Whitney) 01/03/01...
***815 (Solano) 06/19/00...
***815e (Solano-2) 06/19/00...
***815em (Solano-?) 10/23/00...
***815ep (Solano-3) c:Nov'00...
***815p (Solano-3) c:Mar'01...
***815g (Solano-3) c:Sep'01...
***815eg (Solano-3) c:Sep'01...
***820 (Camino) 11/15/99...
***820e (Camino-2) 06/05/00...
***830M (Almador) 07/30/01...
***830MP (Almador) 07/30/01...
***830MG (Almador) 07/30/01...
***840 (Carmel) 10/25/99...
***845 (Brookdale) 09/10/01...
***845MP (Brookdale-M) 03/04/02...
***845MZ (Brookdale-M) 03/04/02...
***845E (Brookdale-E) 05/20/02...
***845G (Brookdale-G) 05/20/02...
***845GL (Brookdale-GL) 05/20/02...
***845GE (Brookdale-GE) 10/07/02...
***845PE (Brookdale-PE) 10/07/02...
***845GV (Brookdale-GV) 10/07/02...
***848P (Breeds Hill) c:Aug'03...
***850 (Tehama) 11/20/00...
***850E (Tehama-E) 05/06/02...
***852GM (Montara-GM) 01/14/03...
***852GMV (Montara-GM) ???...
***852PM (Montara-GM) 06/11/03...
***852GME (Montara-GM) 06/11/03...
***854 (?) 04/11/05...
***855GM (Montara-GM) 03/12/03...
***855GME (Montara-GM) 03/12/03...
***855PM (Odem) 03/12/03...
***860 (Colusa) 05/21/01...
***865G (Springdale) 05/21/03...
***865PE (Springdale-PE) 05/21/03...
***865P (Springdale-P) 05/21/03...
***865GV (Springdale-GV) c:Sep'03...
***875P (Canterwood) 04/14/03...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C281/282 Cache Sx/AT (386SX) <08/22/91
***Notes:...
***Info:...
***Configurations:...
***Features:
o Flexible DRAM Banks Configuration
- The 82C281/2 supports 256K, 1M, and 4M memory devices, total
main memory size can be up to 16MB. A total of 12 different
memory configurations are supported.
o Page Mode Operation
- Based on the memory configuration shown above [see datasheet],
the memory control unit inside the 820281/2 performs page mode
of operation with a varying block size of 1k, 2k, or 4k bytes
for 256k, 1M, or 4M DRAMs respectively.
o System BIOS Shadow RAM
- The 820281/2 memory control unit provides shadow RAM feature for
several areas of memory system BIOS, video BIOS, and adapter
BIOS.
o Memory Remapping
- If shadow RAM feature is not utilized for the memory area
between 0D0000H - 0EFFFFH, then memory remapping is possible.
The local DRAM areas, 0A0000H - 0BFFFFH and 0D0000H - 0EFFFFH, a
total of 256 KByte, are remapped to the top of total system
memory. The areas for 0F0000H-0FFFFFH (system BIOS) and
0C000H-0CFFFFH (Video BIOS) are reserved for shadow RAM purpose.
o Flexible Multiplexed DRAM Address
o Cache Control Subsystem
- Direct-mapped posted write cache control function provides a low
cost alternative to enhance the system performance by up to 50%.
In order to simplify the design without increasing the system
cost or decreasing performance, the 82C281/2 has been designed
to support only non-pipeline mode for systems with cache memory.
The 82C281/2 offers the following cache control features:
- Flexible Cache Memory Size
- 4MB Cacheabie main memory by using 16KB low cost SRAM.
- 8MB Cacheable main memory by using 32KB low cost SRAM.
- Cache 16MB main memory by using 64KB low cost SRAM.
- Increase the cache size beyond 64KB up to 512KB
- Cache Line Size 4 Byte
- Burst mode memory prefetch is supported by the 82C281/2.
During cache read miss cycles, the memory control subsystem
will perform two consecutive read cycles to fetch 4 bytes
from main memory before terminating the cycle by sending
RDYO# signal to 3868X.
- Non-Cacheable Area
The non-cacheable areas are predefined as indicated below:
- I/O address space
- memory address between 0A0000H and 0FFFFFH.
- any memory address beyond the current configured memory
size.
- programmable non-cacheable memory area as defined by
82C281/2 internal registers.
- 82C281 Posted Write Cache
- The 820281 supports flexible direct-mapped cache with posted
write through update of main memory. By programming the
internal register, the post write control signals are
provided by the 820281 to support a one level write buffer.
With posted write, the CPU write cycles can be completed in
2 CPU T-States, thereby increasing system performance.
- 820282 Write Through Cache
- The 820282 supports a write-through cache system which
allows the designer to reduce system cost by eliminating two
F244's and two F373‘s with only a slight reduction in system
performance (5-10%).
- AT Bus Control
- The 820281/2 AT bus control unit handles all of the AT bus
operations and the DMA/Refresh arbitration. The AT bus
control unit supports the following features:
- Programmable AT Bus Clock - The AT bus clock, ATCLK. can
be programmed as CLK2/6, which is default, or CLK2/4.
- Turbo Switch - The 820281/2 provides a turbo switch
feature that allows users to change the system clock
speed. A programmable bit will enable or disable this
turbo function. When the turbo function is enabled by
setting reg[14H], bit[1] to 1, the 82C281/2 turbo pin
then determines the system clock speed. A low on the
turbo pin forces the CPU to run at the current AT bus
speed which IS CLK2/6 or CLK2/4.
**82C283 386SX System Controller c:91...
**82C291 SXWB PC/AT Chipset (386SX) c:91...
**82C295 SLCWB PC/AT Chipset (386SX) ?...
**82C381/382 HiD/386 (386DX) c:89...
**82C391/392 386WB PC/AT Chipset (386DX) <Dec90...
**82C461/462 Notebook PC/AT chipset [no datasheet] ?...
**82c463 SCNB Single Ship Notebook c:92...
**82c465MV/A/B Single-Chip Mixed Voltage Notebook Solution <Oct97...
**82C481?/482? HiP/486 & HiB/486 [no datasheet] Oct89...
**82C491/392 486WB PC/AT Chipset <04/21/91...
**82C493/392 486SXWB <10/21/91...
**82C495SX/392SX LCWB PC/AT chipset [no datasheet] ?...
**82C495SLC DXSLC 386/486 Low Cost Write Back c:92...
**82C495XLC PC/AT Chip Set c:93...
**82c496A/B DXBB PC/AT Chipset <Mar92...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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