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**82489DX       Advanced Programmable Interrupt Controller    10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION

The  82489DX  Advanced   Programmable  Interrupt  Controller  provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.

The main  function of the  82489DX is to provide  interrupt management
across all  processors. This  dynamic interrupt  distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in  systems with multiple  I/O subsystems, where  each subsystem
can  have  its  own  set  of  interrupts.   This  chip  also  provides
inter-processor interrupts,  allowing any  processor to  interrupt any
processor or set  of processor. Each 82489DX I/O  init interrupt input
pin is individually  programmable by software as either  edge or level
triggered.  The interrupt vector and interrupt steering information an
be specified  per pin.  A  32-bit wide timer  is provided that  can be
programmed to interrupt the local processor.  the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate  time slice interrupts locally to  that processor.  the
82489DX   provides   32-bit   software    access   to   its   internal
registers. Since no  82489DX register read have any  side effects, the
82489DX registers  can be aliased  to a  user read-only page  for fast
user access (e.g., performance monitoring timers).

The 82489DX  supports a generalized naming/addressing  scheme that can
be tailored by  software to fit a variety of  system architectures and
usage  models.   It  also  supports 8259A  compatibility  by  becoming
virtually  transparent with  regard to  an externally  connected 8259A
style controller, making the 8259A visible to software.

***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
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**IBM AT: MC146818 Real Time Clock                                 <84
***Info:
The MC146818  Real-Time Clock  plus RAM is  a peripheral  device which
includes   the   unique   MOTEL   concept   for   use   with   various
microprocessors,  microcomputers,  and  larger computers.   This  part
combines  three unique  features:  a complete  time-of-day clock  with
alarm and one hundred year calender, a programmable periodic interrupt
and square-wave generator,  and 50 bytes of low-power  static RAM. The
MC146818  uses high-speed  CMOS  technology to  interface  with 1  MHz
processor busses, while consuming very little power.

The  Real-Time Clock  plus RAM  has two  distinct uses.  First,  it is
designed  as a  battery powered  CMOS part  (in an  otherwise NMOS/TTL
system) including  all the common battery backed-up  functions such as
RAM, time,  and calendar.  Secondly, the  MC146818 may be  used with a
CMOS  microprocessor  to  relieve  the  software  of  the  timekeeping
workload  and to  extend  the available  RAM  of an  MPU  such as  the
MC146805E2
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