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**?????  (Profusion)    c:99
Chips:         
Memory Access Controller (MAC)  
Data Interface Buffer (DIB)
CPUs:          8x P-III Xeon Oct
DRAM Types:    SDRAM PC100 2-way Interleave dual channel
Max Mem:       32GB
ECC/Parity:    ECC
AGP speed:     N/A
Bus Speed:     100
PCI Clock/Bus: 1/3 PCI-66/64



**800 series...
*Headland/G2...
**HT12/+/A      Single 286 AT Chip with EMS support            c:Aug90
***Info:
The  HT12, an IBM  PC/AT compatible  chip, supports  the 80286  CPU at
clock speeds  to 16MHz.  This  highly integrated chip  solution offers
high  performance  and  reliability,  with  low  cost,  minimal  power
consumption,  and low  board-space requirements.  It differs  from the
HT11 by the addition of 4 EMS Registers and an EMS Software Driver.

A  fully PC/AT  compatible system  is  implemented with  this chip  by
adding a CPU/NPU, KBD CNTRL, RTC,  BIOS, Memory and a few low cost TTL
devices.

This  chip supports  64K, 256K  and 1M,  x1 and  x4, DRAMs  in config-
urations up  to 4 Meg.   A 12.5MHz 0  wait-state system can  be imple-
mented using  80ns DRAMs  while a 10MHz  0 wait-state  system requires
100ns  DRAMs.  The  memory  controller also  supports  the shadow  RAM
feature and the  Split Memory option.  The Split  Memory option allows
the System RAM located between 640K and 1M to be remapped above top of
memory.

The HT12 contains CPU  and peripheral support functions; including DMA
controllers, a  memory mapper, timer/counters,  interrupt controllers,
and a bus controller.  This  chip replaces board address buffers, data
transceivers,  memory  drivers, parity  generators  and their  support
circuits. This chip is packaged in a 160 pin Flat Pack.

***Configurations:...
***Features:...
**HT18          80386SX Single Chip                            c:Sep91...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92
***Info:...
***Versions:...
***Features:
General Features
o   Support for 4868X/DX/DX2 CPUs
o   System implementation with Headland’s HTK340 chip set and future 
    486 chip sets
o   16, 20, 25 and 33 MHz CPU speeds

Memory Configurations
o   32KB, 64KB, 128KB, 256KB, 512KB & 1MB cache sizes
o   25ns SRAMs required at 33 MHz
o   Asynchronous and synchronous SRAMs are supported
o   Programmable write-protected and non-cacheable regions are 
    supported through the chip set

Architecture
o   Look-Aside
o   Write through
o   Direct mapped
o   Integrated tag comparator
o   Zero wait state cache hits
o   Simultaneous 486 and secondary cache update on read miss
o   486 line burst cycle support
Package & Die
o   84-pin PLCC
o   LSI Logic’s 0.7 micron HCMOS process

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