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**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o High Performance Second Level Cache
- Zero Wait States at 66 MHz
- Two-Way Set Associative
- Writeback with MESI Protocol
- Concurrent CPU Bus and Memory Bus Operation
- Boundary Scan
o Pentium Processor (735\90, 815\100)
- Chip Set Version of Pentium Processor (735\90, 815\100)
- Superscalar Architecture -
- Enhanced Floating Point
- On-Chip 8K Code and 8K Data Caches
- See Pentium Processor Family Data Book for More Information
o Highly Flexible
- 256K to 512K with Parity
- 32-, 64-, or 128-Bit Wide Memory Bus
- Synchronous, Asynchronous and Strobed Memory Bus Operation
- Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o Full Multiprocessing Support
- Concurrent CPU, Memory Bus and Snoop Operations
- Complete MESI Protocol
- Internal/External Parity Generation/Checking
- Supports Read For Ownership, Write-Allocation and Cache-to-Cache
Transfers
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98
Note, Marlinespike is technically the name of the MS440GX motherboard
Chips:
[82443GX] (PAC) [82371EB] (PIIX4E)
CPUs: Single or Dual P-II/P-III/P-II Xeon/P-III Xeon
DRAM Types: SDRAM Reg SDRAM
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit 128Mbit 256Mbit
Max Mem: 2GB
ECC/Parity: Both
AGP speed: 1x 2x
Bus Speed: 100
PCI Clock/Bus: 1/3
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88
***Info:...
***Versions:...
***Features:...
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*Unresearched:...
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