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**82485       Turbo Cache (and 485Turbocache)                      c90
***Notes:...
***Info:...
***Versions:...
***Features:...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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**UM82C852     Multi I/O For XT                                    <91
***Info:...
***Versions:...
***Features:
o   Supports game port
o   Supports 2nd serial port
o   Centronics printer interface
o   Independent control of transmit, receive, line status and data set 
    interrupts
o   Individual modem control signals
o   Programmable serial interface characteristics:
    — 5, 6, 7 , or 8 bit characters
    — Even, odd or no-parity bit generation and detection
    — 1, 1-1/2, or 2 stop bit generation
o   Milliseconds through month counters for real time clock 56 bits of
    RAM 
    with comparator for comparing the real time counter to the RAM 
    data
o   POWER DOWN input that disables all inputs and outputs
o   Disables the chip from the reset of the system for standby low 
    power operation by use of a POWER DOWN input
o   32,768 Hz crystal for real time clock
o   Four-year calendar (no leap year)
o   24-hour clock

**UM82C206     Integrated Peripheral Controller                    <91...
**UM82c45x     Serial/Parallel chips                                 ?...
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