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**82396SX Smart Cache 12/17/90
***Notes:...
***Info:
The 82396SX Smart Cache (part number 82396SX) is a low cost, single
chip, 16-bit peripheral for Intel's i386 SX Microprocessor. By
storing frequently accessed code or data from main memory the 82396SX
Smart Cache enables the i386 SX Microprocessor to run at near zero
wait states. The dual bus architecture allows another bus master to
access the System Bus while the i386 SX Microprocessor operates out of
the 82396SX Smart Cache on the Local Bus. The 82396SX Smart Cache has
a snooping mechanism which maintains cache coherency with main memory
during these cycles.
The 823968X Smart Cache is completely software transparent, protecting
the integrity of system software. The advanced architectural features
of the 82596SX Smart Cache offer high performance with a cache data
RAM size that can be integrated on a single chip, offering the board
space and cost savings needed in an i386 SX Microprocessor based
system.
1.0 823968X SMART CACHE FUNCTIONAL OVERVIEW
1.1 Introduction
The primary function of a cache is to provide local storage for freq-
uently accessed memory locations. The cache intercepts memory
references and handles them directly without transferring the request
to the System Bus. This results in lower traffic on the System Bus and
decreases latency on the Local Bus. This leads to improved performance
for a processor on the Local Bus. It also increases potential system
performance by reducing each processor's demand for System Bus band-
width, thus allowing more processors or system masters in the system.
By providing fast access to frequently used code and data the cache is
able to reduce the average memory access time of the i386 SX
Microprocessor based system.
The 82396SX Smart Cache is a single chip cache subsystem specifically
designed for use with the i386 SX Microprocessor. The 82396SX Smart
Cache integrates 16KB cache, the Cache Directory and the cache control
logic onto one chip. The cache is unified for code and data and is
transparent to application software. The 82396SX Smart Cache provides
a cache consistency mechanism which guarantees that the cache has the
most recently updated version of the main memory. Consistency sup-
port has no performance impact on the i386 SX Microprocessor. Section
1.2 covers all the 82396SX Smart Cache features.
The 82396SX Smart Cache architecture is similar to the i486 SX
Microprocessor's on-chip cache. The cache is four Way SET associative
with Pseudo LRU (Least Recently Used) replacement algorithm. The line
size is 16B and a full line is retrieved from the memory for every
cache miss. A TAG is associated with every 16B line. The 82396SX Smart
Cache architecture allows for cache read hit cycles to run on the
Local Bus even when the System Bus is not available. 82396SX Smart
Cache incorporates a new write buffer cache architecture, which allows
the i386 SX Microprocessor to continue operation without waiting for
write cycles to actually update the main memory.
A detailed description of the cache operation and parameters is
included in Chapter 2.
The 82396SX Smart Cache has an interface to two electrically isolated
busses. The interface to the i386 SX Microprocessor bus is referred to
as the Local Bus (LB) interface. The interface to the main memory and
other system devices is referred to as the 82396SX Smart Cache System
Bus (SB) interface. The SB interface emulates the i386 SX
Microprocessor. The SB interface, as does the i386TM SX Micro-
processor. operates in pipeline mode.
In addition, it is enhanced by an optional burst mode for Line Fills.
The burst mode provides faster line fills by allowing consecutive read
cycles to be executed at a rate of up to one word per clock
cycle. Several bus masters (or several 82396SX Smart Caches) can share
the same System Bus and the arbitration is done via the SHOLD/SHLDA
mechanism (similar to the i486 SX Microprocessor).
Cache consistency is maintained by the SAHOLD/SEADS# snooping
mechanism, similar to the i486 SX Microprocessor. The 82396SX Smart
Cache is able to run, a zero wait state i386 SX Microprocessor
non-pipelined read cycle if the data exists in the cache. Memory write
cycles can run with zero wait states if the write buffer is not full.
The 82396SX Smart Cache organization provides a higher hit rate than
other standard configurations. The 82396SX Smart Cache, featuring the
new high performance write buffer cache architecture, provides full
concurrency between the electrically isolated Local Bus and System
Bus. This allows the 82396SX Smart Cache to service read hit cycles on
the Local Bus while running line fills or buffered write cycles on the
System Bus.
1.2 Features
1.2.1 823858X-LIKE FEATURES
o The 82396SX Smart Cache maps the entire physical address range of
the i386 SX Microprocessor (16MB) into an 16KB cache. Unified code
and data cache.
o Cache attributes are handled by hardware. Thus the 82396SX Smart
Cache is transparent to application software. This preserves the
integrity of system software and protects the users software
investment.
o Word and Byte writes, Word reads.
o Zero wait states in read hits and in buffered write cycles. All i386
SX Microprocessor cycles are non-pipelined (Note: The i386 SX
Microprocessor must never be pipelined when used with the 82396SX
Smart Cache - NA# must be tied to Vcc).
o A hardware cache FLUSH# option. The 82396SX Smart Cache will
invalidate all the Tag Valid bits in the Cache Directory and clear
the System Bus line buffer when FLUSH# is activated tor a minimum of
four CLK’s.
o The 82396SX Smart Cache supports non-cacheable accesses.
o The 82396SX Smart Cache internally decodes the i387 SX Math
Coprocessor accesses as Local Bus cycles.
o The System Bus interface emulates a i386 SX Microprocessor
interface.
o The 82396SX Smart Cache supports pipelined and non-pipelined system
interface.
o Provides cache consistency (snooping): The 82396SX Smart Cache
monitors the System Bus address via SEADS# and invalidates the cache
address if the System Bus address matches a cached location.
1.2.2 NEW FEATURES
o 16KB on chip cache arranged in four banks, one bank for each way. In
Read hit cycles, one word is read. In a write hit cycle, any byte
within the word can be written. In a cache fill cycle, the whole
line (16B) is written. This large line size increases the hit rate
over smaller line size caches.
o Cache architecture similar to the i486 SX Microprocessor cache: 4
Way set associative with Pseudo LRU replacement algorithm. Line
size is 16B and a full line is retrieved from memory for every cache
miss. A Tag Valid Bit and a Write Protect Bit are associated with
every Line.
o New write buffer architecture with four word deep write buffer
provides zero wait state memory write cycles. I/O, Halt/ Shutdown
and LOCK#ed writes are not buffered.
o Concurrent Line Buffer Cacheing: The 82396SX Smart Cache has a line
buffer that is used as additional memory. Before data gets written
to the cache memory at the completion of a Line Fill it is stored in
this buffer. Cache hit cycles to the line buffer can occur before
the line is written to the cache.
o In i387 SX Math Coprocessor accesses, the 82396SX Smart Cache drives
the READYO# in one wait state if the READYI# was not driven in the
previous clock.
Note that the timing of the 82396SX Smart Cache’s READYO# generation
for i387 SX Math Coprocessor cycles is incompatible with 80287
timing.
o An enhanced System Bus interface:
a) Burst Option is supported in line-fills similar to the i486 SX
Microprocessor. SBRDY# (System Burst READY) is provided in
addition to SRDY#. A burst is always a 16 byte line fill (cache
update) which is equivalent to eight word cycles.
b) System cacheability attribute is provided (SKEN#). SKEN# is used
to determine whether the current cycle is cacheable. It is used
to qualify Line Fill requests.
c) SHOLD/SHLDA system bus arbitration mechanism is supported. A
Multi i386 SX 82396SX Smart Cache cluster can share the same
System Bus via this mechanism.
f) Cache invalidation cycles supported via SEAD$#. This is used to
provide cache coherency.
o Full Local Bus/System Bus concurrency is attained by:
a) Servicing cache read hit cycles on the Local Bus while completing
a Line Fill on the System Bus. The data requested by the i386 SX
Microprocessor is provided over the local bus as the first word
of the Line Fill.
b) Servicing cache read hit cycles on the Local Bus while executing
buffered write cycles on the system bus.
c) Servicing cache read hit cycles on the Local Bus while another
bus master is running (DMA, other i386 SX Microprocessor, 82396SX
Smart Cache, i486 SX Microprocessor, etc...) on the System Bus.
d) Buffering write cycles on the Local Bus while the system bus is
executing other cycles. Write protected areas are supported by
the SWP# input. This enables caching of ROM space or shadowed ROM
space.
o No Post Input (NPI#) provided for disabling of write buffers per
cycle. This option supports memory mapped l/O designs.
o Byte Enable Mask (BEM) is provided to mask the processor byte
enables during a memory read cycle.
o A2oM# input provided for emulation of 8086 address wrap-around.
o SRAM test mode, in which the TAGRAM and the cache RAM are treated as
standard SRAM, is provided. A Tristate Output test mode is also pro-
vided for system debugging. In this mode the 82396SX Smart Cache is
isolated from the other devices in the board by floating all its
outputs.
o Single chip, 132 lead PQFP package, 1 micron CHMOS-IV technology.
***Versions:...
***Features:...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91
***Notes:...
***Info:
The 50 MHz Intel486 DX CPU-Cache Chip Set provides a high performance
solution for servers and high-end desktop systems. This binary
compatible solution has been optimized to provide 50 MHz, zero wait
state performance. The CPU-Cache chip set combines the 50 MHz Intel486
Microprocessor with the 82495DX/82490DX cache subsystem. It delivers
integer performance of 41 V1.1 Dhrystone MlPs and a SPEC integer
rating of 27.9. The cache subsystem features the 82495DX Cache
Controller and the 82490DX Dual Ported Data RAM. Dual ported buffers
and registers of the 82490DX allow the 82495DX Cache Controller to
concurrently handle CPU bus, memory bus, and internal cache operations
for maximum performance.
The CPU-Cache Chip Set offers many features that are ideal for multi-
processor based systems. The Write-Back feature provides efficient
memory bus utilization by reducing bus traffic through eliminating
unnecessary writes to main memory. The CPU-Cache chip set also
supports MESI protocol and monitors the memory bus to guarantee cache
coherency.
The 50 MHz Intel486 DX CPU and 82495DX/82490DX Cache subsystem are
produced on Intel's latest CHMOS V process which features submicron
technology and triple layer metal.
3.0 ARCHITECTURAL OVERVIEW
3.1 Introduction
The Intel486 CPU-cache chip set provides a tightly coupled processing
engine based on the Intel486 microprocessor and a cache subsystem
comprised of the 82495DX cache controller and multiple 82490DX cache
components. Figure 3.1 [see datasheet] diagrams the basic config-
uration.
The cache subsystem provides a gateway between the CPU and the memory
bus. All CPU accesses that can be serviced locally are transparent to
the memory bus and serve to avoid bus traffic. As a result, the cache
chip set reduces memory bus bandwidth to both increase Intel486
processor performance and support efficient multiprocessor systems.
The cache subsystem also decouples the CPU from the memory bus to
provide zero-wait-state operation at high clock frequencies while
allowing relatively slow and inexpensive memories.
The CPU-cache chip set prevents latency and bandwidth bottlenecks
across a variety of uniprocessor and multiprocessor designs. The
processor’s on-chip cache supports a very wide CPU data bus and
high-speed data movement. The second-level cache greatly extends the
capabilities of the on-chip cache resources, enabling a larger portion
of memory cycles to be satisfied independently of the memory bus.
3.2 CPU-Cache Chip Set Description
The chip set is comprised of three functional blocks:
3.2.1 CPU
The chip set includes a special version of the Intel486DX micropro-
cessor at 50 MHz. The Intel486DX Microprocessor Data Sheet provides
complete component specifications.
3.2.2 CACHE CONTROLLER
The 82495DX cache controller is the main control element for the chip
set. providing tags and line states. and determining cache hits and
misses. The 82495DX executes all CPU bus requests and coordinates all
main memory accesses with the memory bus controller (MBC).
The 82495DX controls the data paths of the 82490DX cache components
for cache hits and misses and furnishes the CPU with needed data. The
controller dynamically adds wait states as needed using the most
recently used (MRU) prediction algorithm.
The 82495DX also performs memory bus snoop operations in shared memory
systems and drives the cycle address and other attributes during
memory bus accesses. Figure 3.2 [see datasheet] diagrams the 82495DX.
3.2.3 CACHE SRAM
Multiple 82490DX cache components provide the cache SRAM and data
path. Each component includes the latches, muxes and logic needed to
work in lock step with the 82495DX to efficiently serve both hit and
miss accesses. The 82490DX components take full advantage of VLSI
silicon flexibility to exceed the capabilities of discrete
implementations. The 82490DX components support zero-wait-state hit
accesses and concurrent CPU and memory bus accesses, and they
replicate MRU bits for autonomous way prediction. During memory bus
cycles. the 82490DX components act as a gateway between CPU and memory
buses. Figure 3.3 [see datasheet] diagrams an 82490DX cache component.
3.3 Secondary Cache Features
The 82495DX cache controller and 82490DX cache components provide a
unified, software transparent secondary data and instruction cache.
The cache enables a highspeed processor core that provides efficient
performance even when paired with a significantly slower memory bus.
The secondary cache interprets CPU bus cycles and can service most
memory read and write cycles without accessing main memory. I/O and
other special cycles are passed directly to the memory bus. The cache
has a dual-port structure that permits concurrent CPU and memory bus
operation.
The 82495DX cache controller contains the 8K tag entries and logic
needed to support a cache as large as 256K. Combinations of between 4
and 9 82490DX cache SRAMs are used to create caches ranging from 128K
to 256K, with or without data parity.
The MBC provides logic needed to interface the CPU, 82495DX and
82490DX to the memory bus. Because the MBC also affects system
performance. its design can be the basis of product differentiation.
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82c496A/B DXBB PC/AT Chipset <Mar92
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82C496/7 DXBB PC/AT Chipset (Cached) <01/16/92...
**82C498 DXWB PC/AT chipset [no datasheet] ?...
**82C499 DXSC DX System Controller c:93...
**82C546/547 Python PTM3V c:94...
**82C556/7/8 Viper [no datasheet] ?...
**82C556/7/8N Viper-N Viper Notebook Chipset <05/25/95...
**82C556M/7M/8E Viper-N+ Viper Notebook Chipset c:96...
**82C566/7/8 Viper-Max Chipset Scalable MultiMedia PC Solution ?...
**82C571/572 486/Pentium c:93...
**82C576/7/8 Viper Xpress [no datasheet] ?...
**82C576/8/9 Viper XPress+ [no datasheet, some info] <01/16/97...
**82C596/597 PTMAWB Pentium Adaptive Write-back (Cobra) c:93...
**82C650/1/2 Discovery (Pentium Pro) [no datasheet] ?...
**82C681/2/6/7 386/486WB EISA c:92...
**82C683 386/486AWB EISA [no datasheet] ?...
**82C693/6/7 Pentium uP Write Back Cache EISA c:93...
**82C700 FireStar c:97...
**82C701 FireStar Plus c:97...
**82C750 Vendetta [no datasheet] ?...
**82c801 SCWB2 DX Single Chip Solution c:92...
**82C802 SCWB2 PC/AT Single Chip [no datasheet] ?...
**82C802G/GP System/Power Management Controller (cached) c:93...
**82C895 System/Power Management Controller (cached) c:Sep94...
**82C898 System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2 Buffer Devices <Nov94...
**82C822 PCIB (VLB-to-PCI bridge) c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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