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**Datasheets:

See:
 http://108.59.254.117/~mR_Slug/pub/datasheets/chipsets/

Regetfully I did not keep them all.

*_IBM...
*ACC Micro...
*ALD...
**93C488         5x86/486 Single Chip PCI controller            <Aug96
***Info:...
***Configurations:...
***Features:
o   Support processor bus up to 50MHz.
    - AMD 5x86-133, 486DX4-120/100, 486DX2-80/66, 486DX-50/40/33/25
    - Cyrix/IBM/ST 5x86-120/100, 486DX4-120/100, 486DX2-80/66/50, 
      486DX-40/33/25
    - TI 486DX4-100, 486DX2-80/66
    - Intel 486DX4-100/75, 486DX2-66, 486DX-40/33/25, 486SX
o   Integrated DRAM controller
    - 1Mbyte to 256Mbyte main memory
    - Non-page mode, Fast page mode, Nibble mode, Write per bit mode, 
      EDO mode DRAM providing flexible timing control
    - Supports for auto detection of memory type including size, 
      refresh cycle.
    - 4 RAS lines for 4 DRAM banks
    - Supports for symmetrical and asymmetrical DRAM addressing
    - Supports RAS only, CBR hidden refresh
    - Supports shadow memory and 384K relocated memory
o   Integrated synchronous cache controller
    - 128Kbyte to 1Mbyte cache
    - Support pipeline/non-pipeline burst SSRAM
    - Support X,1,1,1/X,2,2,2 burst cycle
o   Fast IDE interface
    - Supports up to PIO mode 4 Timings
    - Separate master/slave IDE mode support
    - Supports primary/secondary port address swapping
o   PCI bus controller
    - 4 level host to PCI write buffer
    - Supports host to PCI byte merging
    - Supports two PCI bus master
o   Integrated IPC includes
    - Two 8259 interrupt controllers
    - Two 8237 DMA controllers
    - One 8254 timer/counter
    - RTC
    - Keyboard controller
o   Power management
    - Programmable hardware events
    - Programmable CPU clock control (STPCLK#)
    - Slow down system clock speed (SLOWDWN#)
o   Single chip 208 pin QFP

*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82497 Cache Controller and multiple 82492 Cache SRAMs combine with
the Pentium processor  (735\90, 810\100) to form a  CPU Cache chip set
designed for high performance servers and function-rich desktops.  The
high-speed interconnect between the  CPU and cache components has been
optimized to  provide zero-wait state  operation. This CPU  Cache chip
set  is fully  compatible with  existing  software, and  has new  data
integrity features for mission critical applications.

The 82497 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82497  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The  82492 is a  customized high-performance  SRAM that  supports 32-,
64-, 128-bit wide memory bus widths, 16-, 32-, and 64-byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82492, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...