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**93C488 5x86/486 Single Chip PCI controller <Aug96
***Info:
ALD93C488 is the worlds first single chip 486/5x86 core logic that
supports Pipeline Burst/Burst (PB) Synchronous SRAM for L2 cache
implementation. This innovative feature results in much superior
performance than the previous generation core logic design that uses
Asynchronous SRAM for L2 cache. ALD93C488 also features one of the
highest integration in the market and requires only DRAM, BIOS and 9
pieces TTL to complete a cost-effective PCI/ISA system that supports
all available 486 pinout CPUs up to bus speed of 50 MHz.
Employing state-of-the-art 0.6 Micron CMOS technology, ALD93C488
integrates the PB Cache Controller, DRAM Controller, ISA Peripheral
Controllers ( Interrupt Controller, DMA Controller, Timer/Counter,
Real-time Clock and Keyboard Controller ), PCI and ISA Interface and
an Enhanced Local Bus IDE Interface into a single 208 QFP ( Quad Flat
Pack ) IC.
Applying the same technique as the latest Pentium systems, the PB
Cache Controller achieves 3,1,1,1 burst cycle with Pipeline Burst
Synchronous SRAM. Write Back Cache Policy is employed for better CPU
bandwidth utilization. Cache size can range from 128 KB to 1 MB. The
DRAM Controller supports Page, Fast Page and EDO DRAM for maximum
compatibility and ultimate performance. Four banks of DRAM, from 1 MB
to 256 MB, can be accessed, with Auto-detection of memory type and
size.
The PCI Interface meets the requirements of PCI Specifications 2.1
(5V). To support PCI cards that have on-board intelligence, two PCI
Bus Masters can be used. In addition to Host-to-PCI Byte Merging, a
4-level Host-to-PCI Write Buffer is designed to ensure maximum system
throughput. The built-in Enhanced Local Bus IDE Interface supports up
to 4 IDE devices (PIO Mode 4 timing). Advanced features like Address
Swapping between Primary and Secondary IDE Ports and separate
Master/Slave modes are implemented. To make computers environmentally
friendly, ALD93C488 is equipped with integrated power management
technique to stop or slow down the CPU.
***Configurations:...
***Features:...
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*Intel...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:
Date source: 1995_Intel_Pentium_Processors_and_Related_Components.pdf
Information taken from:
1995_Intel_Pentium_Processors_and_Related_Components.pdf*
8249x Cache controllers.pdf**
>* Datasheet dated Nov'94
>** Datasheet undated, whole document dated '95
The info and features section have been solely sourced from the first
source. The second source provides far more detail. Additional
information in the configurations section and below have been sourced
from the second.
"Although the 82497 Cache Controller is part of the Pentium processor
(735\90, 815\100, 1000\120, 1110\133) CPU-Cache Chip Set and the 82496
Cache Controller is part of the Pentium Processor (510\60, 567\66)
Chip Set, the two parts are functionally identical except for the
differences noted in this section." - p491
Aside from some minor differences in pin configuration, the main
difference is the direct support for 3.3V processors. This chipset is
still a 5V part. The cache operates at bus speed, max 66MHz.
This chip was used on the Pentium 90MHz CPU complexes of Intel's
Xpress platform. Specifically the BXCPUPENT90 (Single 90MHz, 16
82492s). Also found on IBM 9595/Server 500 Pentium 90MHz complexes.
***Info:...
***Configurations:...
***Features:...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
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**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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**SL9020 Data Controller <oct88
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**SL9025 Address Controller <oct88...
**SL9090 Universal PC/AT Clock Chip <oct88...
**SL9250 Page Mode Memory Controller (16/20MHz 8MB Max) <oct88...
**SL9350 Page Mode Memory Controller (16/20/25MHz 16MB Max) <oct88...
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