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**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93
***Notes:
Information taken from: 82420_PCIset_ISA_and_EISA_Bridges_Mar93.pdf
Intel_Peripheral_Components_1994.pdf*
1995_Intel_Pentium_Processors_and_Related_Components.pdf*2
82378 (Mar-96).pdf
(Errata:1) http://support.intel.com/support/chipsets/420/8510.htm*3
(Errata:2) http://support.intel.com/support/chipsets/420/8511.htm*3
>* datasheet for 82378 is dated Oct'93
>*2 datasheet for 82378 is dated Dec'94
>*3 see archived sources at the end of this section
The March '93 source makes no mention of the ZB variant, indicating
it was released after this date. The Oct'93 datasheet is only 2
pages, a full length version could not be found. Most differences
between the Mar'93 and the Oct'93 are indicated in the text. In
addition, the Mar'93 refers to the 82378IB specifically, the Oct'93
refers to the 82378 in general, and briefly explains the differences
between the IB and ZB variants.
The main difference between the IB and ZB variants is the number of
supported PCI masters and interrupts. The mar'93 datasheet claims that
the IB variant supports four. The Oct'93 source updates this by
claiming it only supports two and states that only the ZB variant
supports four. Perhaps the Mar'93 datasheet is a misprint, or the
chip didn't meet it's intended specification.
In Errata:1, more specifics are given. Dated Aug'93 the following
diff- erences are given:
"
82378IB * Name change from 82378IB to 82378ZB
Changes: * ZB eliminates all known IB errata
* Features/Enhancements include: Interrupt Steering Logic,
System Management Mode (SMM), leadframe change from copper
to Alloy 42.
Timing:
We anticipate production shipments for the 82378ZB to begin in
December 1993..."
Errata:2 gives further details. The document itself is undated, but
Errata:1 is hyperlinked to it. Its text is quoted in the Versions
section.
The Dec'94 datasheet makes no mention of either variant, it just
refers to the 82378. It would appear that this is the ZB variant. The
biggest change is again to the PCI masters. Now it supports 6 PCI
masters and still 4 PCI interrupts. It also now supports Advanced
Power Management. Differences are shown in the text. There are some
additional insignificant minor differences in the text not shown.
The Mar'96 datasheet again refers to the 82378ZB specifically. This
indicates that the chip described in the Dec'94 is *likely* the ZB
variant. This datasheet describes the 82378ZB and the 82379AB. Changes
in this datasheet have not been added to the quoted text below.
Archived sources:
http://web.archive.org/web/20000816013859/http://support.intel.com/support/chipsets/420/8510.htm
http://web.archive.org/web/20000816013854/http://support.intel.com/support/chipsets/420/8511.htm
***Info:...
***Versions:...
***Features:...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
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**SL82C365 Cache Controller (for 386DX/SX) c:91
***Info:...
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***Features:...
**SL82C465 Cache Controller (for 486/386DX/SX) c:91...
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