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**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97
***Notes:...
***Info:...
***Versions:...
***Features:
o Supported Kits for both Pentium and Pentium II Microprocessors
- 82430TX ISA Kit
- 82440LX ISA/DP Kit
o Multifunction PCI to ISA Bridge
- Supports PCI at 30 MHz and 33 MHz
- Supports PCI Rev 2.1 Specification
- Supports Full ISA or Extended I/O (EIO) Bus
- Supports Full Positive Decode or Subtractive Decode of PCI
- Supports ISA and EIO at 1/4 of PCI Frequency
o Supports both Mobile and Desktop Deep Green Environments
- 3.3V Operation with 5V Tolerant Buffers
- Ultra-low Power for Mobile Environments Support
- Power-On Suspend, Suspend to RAM, Suspend to Disk, and Soft-
OFF System States
- All Registers Readable and Restorable for Proper Resume
from 0.V Suspend
o Power Management Logic
- Global and Local Device Management
- Suspend and Resume Logic
- Supports Thermal Alarm
- Support for External Microcontroller
- Full Support for Advanced Configuration and Power Interface
(ACPI) Revision 1.0 Specification and OS Directed Power
Management
o Integrated IDE Controller
- Independent Timing of up to 4 Drives
- PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec
- Supports "Ultra DMA/33" Synchronous DMA Mode Transfers up to
33 Mbytes/sec
- Integrated 16 x 32-bit Buffer for IDE POI Burst Transfers
- Supports Glue-less "Swap-Bay" Option with Full Electrical
Isolation
o Enhanced DMA Controller
- Two 82C37 DMA Controllers
- Supports PCI DMA with 3 PC/PCI Channels and Distributed DMA
Protocols (Simultaneously)
- Fast Type-F DMA for Reduced PCI Bus Usage
o Interrupt Controller Based on Two 82C59
- 15 Interrupt Support
- Independently; Programmable for Edge/Level Sensitivity
- Supports Optional I/O APIC
- Serial Interrupt Input
o Timers Based on 82C54
- System Timer, Refresh Request, Speaker Tone Output
o USB
- Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec
- Supports Legacy Keyboard and Mouse Software with USB-based
Keyboard and Mouse
- Supports UHCI Design Guide
o SMBus
- Host Interface Allows CPU to Communicate Via SMBus
- Slave Interface Allows External SMBus Master to Control
Resume Events
o Real-Time Clock
- 256-byte Battery-Back CMOS SRAM
- Includes Date Alarm
- Two 8-byte Lockout Ranges
o Microsoft Win95 Compliant
o 324 mBGA Package
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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*TI (Texas Instruments)...
**SN74LS610/2 IBM AT: SN74LS610, SN74LS612 Memory Mappers <84
***Notes:...
***Info:
Each 'LS610 and 'LS612 memory mapper integrated circuit contains a
4-line to 16-line decoder, a 16-word by 12-bit RAM, 16 channels of
2-line to 1-line multiplexers, and other miscellaneous circuitry on a
monolithic chip. Each 'LS610 also contains 12 latches with an enable
control.
The memory mappers are designed to expand a microprocessor's memory
addressing capability by eight bits. Four bits of the memory address
bus (see System Block Diagram)[see datasheet] can be used to select
one of 16 map registers that contain 12 bits each. these 12 bits are
presented to the system memory address bus through the map output
buffers along with the unused memory address bits from the CPU.
However, addressable memory space without reloading the map registers
is the same as would be available with the memory mapper left out.
The addressable memory space is increased only by periodically
reloading the map registers from the data bus. This configuration
lends itself to memory utilization of 16 pages of 2^(n-4) registers
each without reloading (n - number of address bits available from
CPU).
These devices have four modes of operation: read, write, map, and
pass. Data may be read from or loaded into the map register selected
by the register select inputs (RS0 thru RS3) under control of R/W
whenever chip select (CS) is low. The data I/O takes place on the data
bus DO thru D7. The map operation will output the contents of the map
register selected by the map address inputs (MA0 thru MA3) when CS is
high and MM (map mode control) is low. The 'LS612 output stages are
transparent in this mode, while the 'LS610 outputs may be transparent
or latched. When CS and MM are both high (pass mode), the address bits
on MA0 thru MA3 appear at M08-MO11, respectively (assuming appropriate
latch control) with low levels in the other bit positions on the map
outputs.
***Versions:...
***Features:...
**TACT82000 3-Chip 286 [no datasheet] c89...
**TACT82411 Snake Single-Chip AT Controller c90...
**TACT82S411 Snake+ Single-Chip AT Controller [no datasheet] c91...
**TACT83000 AT 'Tiger' Chip Set (386) c89...
**TACT84500 AT Chip Set (486, EISA) [no datasheet, some info] c91...
**Other:...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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