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**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97
***Notes:...
***Info:...
***Versions:...
***Features:
o Supported Kits for both Pentium and Pentium II Microprocessors
- 82430TX ISA Kit
- 82440LX ISA/DP Kit
o Multifunction PCI to ISA Bridge
- Supports PCI at 30 MHz and 33 MHz
- Supports PCI Rev 2.1 Specification
- Supports Full ISA or Extended I/O (EIO) Bus
- Supports Full Positive Decode or Subtractive Decode of PCI
- Supports ISA and EIO at 1/4 of PCI Frequency
o Supports both Mobile and Desktop Deep Green Environments
- 3.3V Operation with 5V Tolerant Buffers
- Ultra-low Power for Mobile Environments Support
- Power-On Suspend, Suspend to RAM, Suspend to Disk, and Soft-
OFF System States
- All Registers Readable and Restorable for Proper Resume
from 0.V Suspend
o Power Management Logic
- Global and Local Device Management
- Suspend and Resume Logic
- Supports Thermal Alarm
- Support for External Microcontroller
- Full Support for Advanced Configuration and Power Interface
(ACPI) Revision 1.0 Specification and OS Directed Power
Management
o Integrated IDE Controller
- Independent Timing of up to 4 Drives
- PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec
- Supports "Ultra DMA/33" Synchronous DMA Mode Transfers up to
33 Mbytes/sec
- Integrated 16 x 32-bit Buffer for IDE POI Burst Transfers
- Supports Glue-less "Swap-Bay" Option with Full Electrical
Isolation
o Enhanced DMA Controller
- Two 82C37 DMA Controllers
- Supports PCI DMA with 3 PC/PCI Channels and Distributed DMA
Protocols (Simultaneously)
- Fast Type-F DMA for Reduced PCI Bus Usage
o Interrupt Controller Based on Two 82C59
- 15 Interrupt Support
- Independently; Programmable for Edge/Level Sensitivity
- Supports Optional I/O APIC
- Serial Interrupt Input
o Timers Based on 82C54
- System Timer, Refresh Request, Speaker Tone Output
o USB
- Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec
- Supports Legacy Keyboard and Mouse Software with USB-based
Keyboard and Mouse
- Supports UHCI Design Guide
o SMBus
- Host Interface Allows CPU to Communicate Via SMBus
- Slave Interface Allows External SMBus Master to Control
Resume Events
o Real-Time Clock
- 256-byte Battery-Back CMOS SRAM
- Includes Date Alarm
- Two 8-byte Lockout Ranges
o Microsoft Win95 Compliant
o 324 mBGA Package
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90, 815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich desktops. The high-speed interconnect between the CPU
and cache components has been optimized to provide zero-wait state
operation. This CPU Cache chip set is fully compatible with existing
software, and has new data integrity features for mission critical
applications.
The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82498 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit wide memory bus widths, 32-, and 64-byte line sizes, and
optional sectoring. The data path between the CPU bus and memory bus
is separated by the 82493, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:
***440FX (Natoma) 05/06/96...
***440LX (Balboa) 08/27/97...
***440BX (Seattle) c:Apr'98...
***440DX (?) c:?...
***440EX (?) c:Apr'98...
***440GX (Marlinespike) 06/29/98...
***440ZX & 440ZX-66 (?) 01/04/99...
***440ZX-M (?) 05/17/99...
***440MX (Banister) 05/17/99...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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