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**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95
***Notes:...
***Info:
The 82371MX PCI I/O IDE Xcelerator (MPIIX) provides the bridge between
the PCI bus and the  ISA-like Extended I/O expansion bus. In addition,
the  82371MX  has an  IDE  interface  that  supports two  IDE  devices
providing  an interface  for IDE  hard disks  and CD  ROMS.  The MPIIX
integrates many common  I/O functions found in ISA  based PC systems-a
seven-channel DMA controller, two 82C59 interrupt controllers. an 8254
timer/counter, Intel  SMM power management support,  and control logic
for NMI  generation. Chip select  decoding is provided for  BIOS, real
time  clock,  and   keyboard  controller.  Edge/Level  interrupts  and
interrupt steering are supported for PCI plug and play compatibility.

The MPIIX also  provides the Extended I/O Bus  for a direct connection
to  Super   I/O  devices   providing  a  complete   PC-compatible  I/O
solution.  MPIIX also  provides support  for the  “Mobile  PC/PCI" DMA
Expansion protocol that enables the implementation of Docking Stations
with  full ISA and  PCI capability  without running  the full  ISA bus
across   the   docking    connector.   For   motherboard   Plug-n-Play
compatibility.   the  82371MX  also   provides  three   steerable  DMA
channels. up  to three steerable  interrupt lines, and  a programmable
chip select. The interrupt lines can be routed to any of the available
ISA interrupts.

The MPIIX’s power management function supports SMI# interrupt sources,
extensive clock control  (including Auto Clock Throttling), peripheral
power  idle detection  with access  traps. system  Suspend-to-DRAM and
Suspend-to-Disk.

***Versions:...
***Features:...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**?????  (Profusion)    c:99...
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**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91
***Info:
The SL82C465 cache controller supports both 1X and 2X clock modes. The
1X clock  mode means that the CCLK2  signal is used as  the CPU clock;
the 2X clock  mode means that the PCLK signal  (half the frequency and
the phase indicator  of CCLK2) is used as the  CPU clock. The SL82C465
and other CPU local bus devices run at the same clock frequency as the
CPU, while  the rest of the system  runs at the frequency  of PCLK. In
other words, the operating frequency of the system logic is either the
same (2X clock mode) or half the speed of the CPU (1X clock mode). For
the 1X clock mode, the timing of the signals between the CPU/Cache and
the system logic interface  is converted by the SL82C465 automatically
to  satisfy  the requirement  of  individual  clocks.  Table 1-1  [see
datasheet] lists  the operating frequencies  of the CPU local  bus and
the system logic with the oscillator used.

The 2X  clock mode is recommended  for a CPU frequency  no faster than
33Mhz because the system logic  is available at the targeted speed and
the  performance  is  slightly  better  than if  1X  clock  mode  were
used. For  a CPU  frequency faster  than 33Mhz, the  1X clock  mode is
preferred  for  486  systems  because  it  becomes  increasingly  more
difficult to  build a reliable  system with an oscillator  faster than
66Mhz.

***Versions:...
***Features:...
*TI (Texas Instruments)...
*UMC...
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