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**M1489/87 FinALi-486 PCI Chipset <Feb95
***Info:...
***Configurations:...
***Features:
Supported CPUs
o Supports AMD 486D4 and X5, Intel 486, P24T, P24D, DX4, SL-
Enhanced, Cyrix M7, UMC U5 and AMD AM486DXL CPUs in 25, 33, 40,
50, 66, 100 and 133 MHz 3V/5V CPU interface
o Supports CPU L1 writeback
o Supports Cyrix's linear addressing
L2 Cache Controller
o Write Back cache with standard SRAM
o 8 Tag Bit, always force Dirty or 7 Tag Bit, 1 Dirty bit
o Supports cache size of 128K to 1M with 32KX8, 64Kx8, 128Kx8
o Supports 2-1-1-1 read burst timing
o Write hit 0 wait support
DRAM Controller
o Supports 5V/3V EDO DRAM
o Flexible DRAM type & Timing support
o Supports up to 128M bytes, 4-bank DRAM size
o Supports hidden refresh and RAS only normal refresh
Built in RTC & KBC
o Built in 128 byte Real Time Clock (RTC) & MC14069
o Built in Keyboard Controller (KBC) & 7406
Built in IDE Controller
o Dedicated IDE pins, concurrent with PCI bus
o 4x32 bits Read-Ahead buffer and Write-Post buffer support
o Supports through ATA PIO mode 3, 4 harddisk
PCI Local Bus
o Synchronous 20, 25, 33 MHz PCI clock
o Supports PCI rev 2.0 with 4 PCI devices, 3 slot PCI masters, 1
slot PCI slave
o Supports 4 PCI interrupt steering input
o Supports CPU to PCI 4 layer DWord write buffer
o Supports PCI to memory 8 layer DWord write buffer
o Supports PCI parity
Power Management
o Deep Green SMM, SMI
o Suspend switch support, Green mode state is LED indicated
o CLKCTR for clock generator control
Process/Packing
o M1489 0.6u, 208-pin PQFP
o M1487 0.6u, 160-pin PQFP
**M???? Genie, Quad Pentium [no datasheet, some info] c95...
**M1451/49 Aladdin (Pentium) [no datasheet] ?...
**M1511/12/13 Aladdin II (Pentium) [no datasheet, some info] >Apr95...
**M1521/23 Aladdin III 50-66MHz <Nov96...
**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84
***Notes:...
***Info:...
***Versions...
***Features:...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor to form a CPU Cache chip set designed for high
performance servers and function-rich desktops. The high speed
interconnect between the CPU and cache components has been optimized
to provide zero-wait state operation. This CPU Cache chip set is
fully compatible with existing software, and has new data integrity
features for mission critical applications.
The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82496 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit wide memory bus widths, 16, 32, and 64 byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82491, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
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