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**82420EX PCIset (for 486) EX (Aries) (82425EX/82426EX) <Dec94
***Notes:...
***Info:...
***Configurations:...
***Features:
o Host CPU
- 25-33 MHz Intel486 and OverDrive Processors
- L1 Write-Back Support
o Integrated DRAM Controller
- 1 to 128 MByte Main Memory
- 70 ns Fast Page Mode DRAM SIMMs Supported
- Supports 256 KByte, 1 MByte, and 4 MByte Double and Single Sided
SIMMs
- Read Page Hit Timing of 3-2-2-2 at 33 MHz
- Burst Mode PCI Master Accesses
- Decoupled Refresh Reduces DRAM Latency
- Five RAS Lines
o Integrated L2 Cache Controller
- Write-Back and Write-Through Cache Policies
- Direct Mapped Organization
- 64, 128, 256 or 512 KByte Cache Sizes
- Programmable Zero Walt-State L2 Cache Read and Write Accesses
- Two Banks Interleaved or a Single Bank Non-Interleaved Operation
- No VALID Bit Required
o 25/33 MHz PCI Bus Interface
- Two Bus Masters
- PCI Auto Configuration Support
o Host/PCI Bridge
- Converts Back-to-Back Sequential Memory Writes to PCI Burst
Writes
- CPU Memory Write Posting to PCI
o PCI Local Bus IDE Interface
- Supports Mode 3 Timing
o Programmable Attribute Map for First 1 MByte of Main Memory
o 100% ISA Compatible
- Directly Drives 5 ISA Slots
o Two 8237 DMA Controllers
- 7 DMA Channels
- 27-bit Addressability
- Compatible DMA Transfers
o One 82C54 Timer/Counter
- System Timer
- Refresh Request
- Speaker Tone
o Two 82C59 Interrupt Controllers
- 14 Interrupts
- Edge/Level Sense Is Programmable per Channel
- PCI Interrupt Steering for Plug and Play Compatibility
o X-Bus Peripheral Support
- RTC, KBC, BIOS Chip Selects
- Control for Lower X-Bus Transceiver
- Integrates Mouse Interrupt
- Coprocessor Error Reporting
o Non-Maskable Interrupts (NMI)
- PCI System Errors
- Main Memory Parity Errors
- ISA Parity Errors
o System Power Management (Intel SMM Support)
- Programmable System Management Interrupt (SMI)-Hardware Events,
Software Events, EXTSMI#
- Programmable CPU Clock Control
- Fast on/off Mode
o Generates System Clocks
o 160-Pin QFP Package for IB
o 208-Pin QFP Package for PSC
**82430LX PCIset (Pentium) LX (Mercury) (82433LX/82434LX) 03/22/93...
**82430NX PCIset (Pentium) NX (Neptune) (82433NX/82434NX) Mar94...
**82430FX PCIset (Pentium) FX (Triton I) (82437FX/82438FX)01/31/95...
**82430MX PCIset (Pentium) MX (Mobile Triton)(82437/438MX)11/01/95...
**82430HX PCIset (Pentium) HX (Triton II) (82439HX) 02/12/96...
**82430VX PCIset (Pentium) VX (Triton II) (82437VX/82438) 02/12/96...
**82430TX PCIset (Pentium) TX (Triton II) (82439TX) 02/17/97...
**82450KX/GX PCIset (Pentium Pro) KX/GX (Mars/Orion) 11/01/95...
**
**Support Chips:
**82091AA Advanced Interface Peripheral (AIP) c93...
**8289 Bus Arbiter (808x) c79...
**82289 Bus Arbiter for iAPX 286 Processor Family c83...
**82258 Advanced Direct Memory Access Coprocessor(ADMA) 01/01/84...
**82335 High-Integration Interface Device For 386SX c:Nov88...
**82360SL I/O Subsystem 10/05/90...
**82370 Integrated System Peripheral (for 82376) c:Oct88...
**82371FB/SB PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 11/01/95...
**82371AB PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4) 02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB) c:Mar93...
**82378 System I/O (SIO) (82378IB and 82378ZB) c:Mar93...
**82379AB System I/O-APIC (SIO.A) <Dec94...
**82380 32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384 Clock Generator and Reset Interface c86...
**82385 32-bit Cache Controller for 80386 09/29/87...
**82385SX 32-bit Cache Controller for 80386SX 01/25/89...
**82395DX High Performance Smart Cache 06/18/90...
**82395SX Smart Cache 12/17/90...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91
***Notes:...
***Info:...
***Features:...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
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*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
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**SL82C465 Cache Controller (for 486/386DX/SX) c:91
***Info:
The SL82C465 cache controller supports both 1X and 2X clock modes. The
1X clock mode means that the CCLK2 signal is used as the CPU clock;
the 2X clock mode means that the PCLK signal (half the frequency and
the phase indicator of CCLK2) is used as the CPU clock. The SL82C465
and other CPU local bus devices run at the same clock frequency as the
CPU, while the rest of the system runs at the frequency of PCLK. In
other words, the operating frequency of the system logic is either the
same (2X clock mode) or half the speed of the CPU (1X clock mode). For
the 1X clock mode, the timing of the signals between the CPU/Cache and
the system logic interface is converted by the SL82C465 automatically
to satisfy the requirement of individual clocks. Table 1-1 [see
datasheet] lists the operating frequencies of the CPU local bus and
the system logic with the oscillator used.
The 2X clock mode is recommended for a CPU frequency no faster than
33Mhz because the system logic is available at the targeted speed and
the performance is slightly better than if 1X clock mode were
used. For a CPU frequency faster than 33Mhz, the 1X clock mode is
preferred for 486 systems because it becomes increasingly more
difficult to build a reliable system with an oscillator faster than
66Mhz.
***Versions:...
***Features:...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
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