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**VT82C598MVP Apollo MVP3,Single-Chip 66/75/83/100MHz & AGP <09/22/97
***Notes:...
***Info:...
***Configurations:...
***Features:
o AGP / PCI / ISA Mobile and Deep Green PC Ready
- Supports 3.3V and sub-3.3V interface to CPU
- Supports separately powered 3.3V (5V tolerant) interface to
system memory, AGP, and PCI bus
- PC-97 compatible using VIA VT82C586B (208-pin PQFP) south bridge
chip with ACPI Power Management for cost-efficient desktop
applications
- Modular power management and clock control for mobile system
applications
- Combine with VIA VT82C596 (Intel PIIX4 pin compatible 324-pin
BGA) "Mobile South" south bridge chip for state-of-the-art
mobile applications
o High Integration
- Single chip implementation for 64-bit Socket-7-CPU, 64-bit
system memory, 32-bit PCI and 32-bit AGP interfaces
- Apollo MVP3 Chipset: VT82C598MVP system controller and
VT82C586B PCI to ISA bridge
- Chipset includes UltraDMA-33 EIDE, USB, and Keyboard / PS2-Mouse
Interfaces plus RTC / CMOS on chip
o High Performance CPU Interface
- Supports all Socket-7 processors including 64-bit Intel Pentium/
Pentium with MMX, AMD 6k86 (K6), Cyrix/IBM 6x86 / 6x86MX, and
IDT/Centaur C6 CPUs
- 66 / 75 / 83 / 100 MHz CPU external bus speed (internal 300MHz
and above)
- Built-in deskew DLL (Delay Lock Loop) circuitry for optimal skew
control within and between clocking regions
- Cyrix/IBM 6x86 linear burst support
- AMD 6k86 write allocation support
- System management interrupt, memory remap and STPCLK mechanism
o Advanced Cache Controller
- Direct map write back or write through secondary cache
- Pipelined burst synchronous SRAM (PBSRAM) cache support
- Flexible cache size: 0K / 256K / 512K / 1M / 2MB
- 32 byte line size to match the primary cache
- Integrated 8-bit tag comparator
- 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access up to
100 MHz
- Tag timing optimized (less than 4ns setup time) to allow
external tag SRAM implementation for most flexible cache
organization
- Sustained 3 cycle write access for PBSRAM access or CPU to
DRAM & PCI bus post write buffers up to 100 MHz
- Supports CPU single read cycle L2 allocation
- System and video BIOS cacheable and write-protect
- Programmable cacheable region
o Full Featured Accelerated Graphics Port (AGP) Controller
- Synchronous and pseudo-synchronous with the host CPU bus with
optimal skew control
PCI AGP CPU DRAM Mode
33MHz 66MHz 100MHz 100MHz 3x synchronous *1
33MHz 66MHz 83MHz 83MHz 2.5x pseudo-synchronous *1
30MHz 60MHz 75MHz 75MHz 2.5x pseudo-synchronous *1
33MHz 66MHz 66MHz 66MHz 2x synchronous *1
33MHz 66MHz 100MHz 66MHz 3x synchronous *2
33MHz 66MHz 83MHz 66MHz 2.5x pseudo-synchronous *2
30MHz 60MHz 75MHz 66MHz 2.5x pseudo-synchronous *2
33MHz 66MHz 66MHz 66MHz 2x synchronous *2
*1 DRAM uses CPU clock, *2 DRAM uses AGP clock
- AGP v2.0 compliant (1x and 2x transfer modes)
- Supports SideBand Addressing (SBA) mode (non-multiplexed
address/data)
- Supports 133MHz 2X mode for AD and SBA signalling
- Pipelined split-transaction long-burst transfers up to 533 MB/
sec
- Eight level read request queue
- Four level posted-write request queue
- Thirty-two level (quadwords) read data FIFO (128 bytes)
- Sixteen level (quadwords) write data FIFO (64 bytes)
- Intelligent request reordering for maximum AGP bus utilization
- Supports Flush/Fence commands
- Graphics Address Relocation Table (GART)
- One level TLB structure
- Sixteen entry fully associative page table
- LRU replacement scheme
- Independent GART lookup control for host / AGP / PCI master
accesses
- Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport
driver support
o Concurrent PCI Bus Controller
- PCI buses are synchronous / pseudo-synchronous to host CPU bus
- 33 MHz operation on the primary PCI bus
- 66 MHz PCI operation on the AGP bus
- PCI-to-PCI bridge configuration on the 66MHz PCI bus
- Supports up to five PCI masters
- Peer concurrency
- Concurrent multiple PCI master transactions; i.e., allow PCI
masters from both PCI buses active at the same time
- Zero wait state PCI master and slave burst transfer rate
- PCI to system memory data streaming up to 132Mbyte/sec
- PCI master snoop ahead and snoop filtering
- Six levels (double-words) of CPU to PCI posted write buffers
- Byte merging in the write buffers to reduce the number of PCI
cycles and to create further PCI bursting possibilities
- Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
- Forty-eight levels (double-words) of post write buffers from PCI
masters to DRAM
- Sixteen levels (double-words) of prefetch buffers from DRAM for
access by PCI masters
- Supports L1/L2 write-back forward to PCI master read to minimize
PCI read latency
- Supports L1/L2 write-back merged with PCI master post-write to
minimize DRAM utilization
- Delay transaction from PCI master reading DRAM
- Read caching for PCI master reading DRAM
- Transaction timer for fair arbitration between PCI masters
(granularity of two PCI clocks)
- Symmetric arbitration between Host/PCI bus for optimized system
performance
- Complete steerable PCI interrupts
- PCI-2.1 compliant, 32 bit 3.3V PCI interface with 5V tolerant
inputs
o Advanced High-Performance DRAM Controller
- DRAM interface synchronous with host CPU (66/75/83/100 MHz) or
AGP (66MHz) for most flexible configuration
- Concurrent CPU and AGP access
- FP, EDO, and SDRAM
- 66MHz and 100MHz (PC100) SDRAM support
- Different DRAM types may be used in mixed combinations
- Different DRAM timing for each bank
- Dynamic Clock Enable (CKE) control for SDRAM power reduction in
mobile and desktop systems
- Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
- 6 banks up to 768MB DRAMs
- Flexible row and column addresses
- 64-bit data width only
- 3.3V DRAM interface with 5V-tolerant inputs
- Programmable I/O drive capability for MA, command, and MD signals
- Optional bank-by-bank ECC (single-bit error correction and
multi-bit error detection) or EC (error checking only) for DRAM
integrity
- Two-bank interleaving for 16Mbit SDRAM support
- Two-bank and four bank interleaving for 64Mbit SDRAM support
- Supports maximum 8-bank interleave (i.e., 8 pages open simultan-
eously); banks are allocated based on LRU
- Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)
- Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers
- Four quadwords of CPU/cache to DRAM read prefetch buffers
- Concurrent DRAM writeback
- Read around write capability for non-stalled CPU read
- Burst read and write operation
- 5-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM
- 6-1-1-1-2-1-1-1 back-to-back accesses for SDRAM
- BIOS shadow at 16KB increment
- Decoupled and burst DRAM refresh with staggered RAS timing
- Programmable refresh rate and refresh on populated banks only
- CAS before RAS or self refresh
o Mobile System Support
- Independent clock stop controls for CPU / SDRAM, AGP, and PCI
bus
- PCI and AGP bus clock run and clock generator control
- VTT suspend power plane preserves memory data
- Suspend-to-DRAM and Self-Refresh operation
- New VIA BGA VT82C596 “Mobile South” south bridge chip available
soon for support of new mobile features
- Dynamic clock gating for internal functional blocks for power
reduction during normal operation
- Low-leakage I/O pads
o Built-in NAND-tree pin scan test capability
o 3.3V, 0.35um, high speed / low power CMOS process
o 35 x 35 mm, 476 pin BGA Package
**VT8501 Apollo MVP4,Single-Chip 66-100MHz & AGP <11/04/98
***Notes:...
***info:
The Apollo MVP4 is a PC Socket-7 system logic North Bridge with
integrated 2D / 3D Graphics accelerator. The core logic portion of
the chip is based on the popular 100MHz VIA Apollo MVP3 chipset with
enhanced features and graphics accelerator based on the Cyber9398DVD
from Trident Microsystems, Inc. The combination of the two leading
edge technologies provides a stable, cost-effective, and high
performance solution for personal computers, embedded systems, set-top
boxes and others. As shown in Figure 1 [see datasheet] below, the
Apollo MVP4 will interface to:
o Socket 7 CPU (66 – 100 MHz)
o L2 Cache RAM & Tag
o SDRAM Memory Interface
o PCI Bus (30 - 33 MHz)
o Analog RGB Monitor with DDC
o DFP / Digital Monitor Interface (TMDS)
o Video Capture / Playback CODECs
Apollo MVP4 Core Logic Overview
The Apollo MVP4 – System Media Accelerated North Bridge (SMA) is a
high performance, cost-effective and energy efficient solution for the
implementation of Integrated 2D/3D Graphics - PCI - ISA personal
computer systems from 66 MHz to 100 MHz based on 64-bit Socket-7
(Intel Pentium and Pentium MMX; AMD K6 and K6-2; Cyrix / National 6x86
/ 6x86MX, IDT / Centaur C6/WinChip), and Rise MP6 processors.
The Apollo MVP4 controller provides superior performance between the
integrated 2D/3D Graphics Engine, CPU, optional synchronous cache,
DRAM, and PCI bus with pipelined, burst, and concurrent operation.
For L2-Cache solutions using pipelined burst synchronous SRAMs,
3-1-1-1-1-1-1-1 timing can be achieved for both read and write
transactions at 100 MHz. Tag timing is specially optimized internally
(less than 4 nsec setup time) to allow implementation of L2 cache
using an external tag for t he most flexible cache organization (0K /
256K / 512K / 1M / 2M). Four cache lines (16 quadwords) of CPU/cache
to DRAM write buffers with concurrent write-back capability are
included on chip to speed up cache read and write miss cycles.
The Apollo MVP4 supports six banks of DRAMs up to 768MB. The DRAM
controller supports standard Fast Page Mode (FP) DRAM, EDO-DRAM,
Synchronous DRAM (SDRAM), and Virtual Channel Synchronous DRAM in a
flexible mix / match manner. The Synchronous DRAM interface allows
zero wait state bursting between the DRAM and the data buffers at 100
MHz. The six banks of DRAM can be composed of an arbitrary mixture of
1M / 2M / 4M / 8M / 16MxN DRAMs. The DRAM controller also supports
optional ECC (single-bit error correction and multi-bit detection) or
EC (error checking) capability separately selectable on a bank-by-bank
basis. The DRAM Controller can run at either the host CPU bus
frequency (66 / 100 MHz) or at the PC100 memory frequency (100 MHz)
with built-in deskew PLL timing control. With the advanced DRAM
controller, the Apollo MVP4 allows implementation of the most
flexible, reliable, and high-performance DRAM interface.
The Apollo MVP4 also supports full AGP v2.0 capability with the
internal 2D/3D Graphics Engine for maximum software compatibility. An
eight level request queue plus a four level post-write request queue
with thirty-two and sixteen quadwords of read and write data FIFO’s
respectively are included for deep pipelined and split AGP
transactions. A single-level GART TLB with 16 full associative
entries and flexible CPU/AGP/PCI remapping control is also provided
for operation under protected mode operating environments. Both
Windows-95 VXD and Windows-98 / NT5 miniport drivers are supported.
The Apollo MVP4 supports one 32-bit 3.3 / 5V system bus (PCI) that is
synchronous / pseudo-synchronous to the CPU bus. The chip also
contains a built-in AGP bus -to- PCI bus bridge to allow simultaneous
concurrent operations on each bus. Five levels (doublewords) of
posted write buffers are included to allow for concurrent CPU and PCI
operation. For PCI master operation, forty-eight levels (doublewords)
of posted write buffers and sixteen levels (doublewords) of prefetch
buffers are included for concurrent PCI bus and DRAM/cache accesses.
The chip also supports enhanced PCI bus commands such as
Memory-Read-Line, Memory-Read-Multiple, and Memory-Write-Invalid
commands to minimize snoop overhead. In addition, advanced features
are supported such as snoop ahead, snoop filtering, L1 write-back
forward to PCI master, and L1 write-back merged with PCI post write
buffers to minimize PCI master read latency and DRAM utilization.
Delayed transaction and read caching mechanisms are also implemented
for further improvement of overall system performance.
The Apollo MVP4 provides independent clock stop control for the CPU /
SDRAM, PCI, and AGP buses and Dynamic CKE control for powering down of
the SDRAM. A separate suspend-well plane is implemented for the SDRAM
control signals for Suspend-to-DRAM operation. Coupled with the
324-pin Ball Grid Array VIA VT82C596B south bridge chip, a complete PC
main board can be implemented with no external TTLs.
The Apollo MVP4 controller coupled with VIA’s highly integrated south
bridge, the VT82C686A, is ideal for high performance, energy
efficient, and highly integrated computer systems. The VT82C686A
supports a PCI-to-ISA bus controller, four USB ports, dual bus-master
IDE with UltraDMA33/66, AC97 basic digital audio, system hardware
monitoring, and integrated "Super-I/O" functionality.
***Configurations:...
***Features:...
**VT82C680 Apollo P6, Pentium-Pro Chip Set <08/30/96...
**Support chips:
**VT82C505 Pentium/486 VL to PCI Bridge <05/30/94...
**VT82C586/A/B PCI Integrated Peripheral Controller <10/13/96...
**VT82C596/A Mobile PCI Integrated Peripheral Controller <11/05/97...
**VT82C686A/B PCI Super-I/O Integrated Peripheral Ctrl. <02/10/98...
**Later P-Pro/II/III/Celeron...
**Later AMD...
**Other...
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