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**82360SL     I/O Subsystem                                   10/05/90
***Notes:...
***Info:...
***Versions:...
***Features:
o   Complete ISA System, with Extended Support 
    - Full ISA Bus Control, Status and Address and Data Interface 
      Logic, with Full 24 mA Drive 
    - Compatible ISA Bus Peripherals: 
      • Two 8237 Direct Memory Access Controllers 
      • Two 8254 Programmable Timer Counters (6 Timer/Counter 
        Channels) 
      • Two 8259A Programmable Interrupt Controllers (15 Channels) 
      • Enhanced LS612 Page Memory Mapper 
      • One 146818 Compatible Real Time Clock w/256-byte CMOS RAM 
      • Two 16450 Compatible Serial Port Controllers 
      • One 8-Bit Parallel I/O Port with High Speed Protocol 
        (Centronics or Bi-Directional) 
    - Additional System I/O Decoding, Programmable Chip Selects and 
      Support Interfaces: 
      • Full Integrated Drive Electronics (I.D.E.) Hard Disk Interface 
      • Floppy Disk Controller 
      • Keyboard Controller Chip Selects and Support Logic 
    - External Real Time Clock Support 
    - PS/2 and EISA Control/Status Ports 
    - Local Memory and ISA-Bus Memory Refresh Control 
    - New ideaPort Interface for Hardware Expansion 
o   Transparent Power-Management System Architecture 
    - Architecture Extension for Truly Compatible Systems 
    - Transparent to Operating Systems and Applications Programs 
    - Programmable Hardware Supports Custom Power-Control Methods 
    - Integrated Power Management Unit Manages Power-Events Safely 



**82370       Integrated System Peripheral (for 82376)         c:Oct88...
**82371FB/SB  PCI ISA IDE Xcelerator 82371FB/82371SB (PIIX/3) 01/31/95...
**82371MX     Mobile PCI I/O IDE Xcelerator (MPIIX)           11/01/95...
**82371AB     PCI-TO-ISA / IDE Xcelerator 82371AB (PIIX4)     02/17/97...
**82374/82375 PCI-EISA Bridge (82374EB/82375EB, 374SB/375SB)   c:Mar93...
**82378       System I/O (SIO) (82378IB and 82378ZB)           c:Mar93...
**82379AB     System I/O-APIC (SIO.A)                           <Dec94...
**82380       32-bit DMA Controller w/ Integrated Peripherals 02/01/87...
**82380FB/AB  PCIset: 82380FB Mobile PCI-to-PCI Bridge(MPCI2) 02/17/97...
**82384       Clock Generator and Reset Interface                  c86...
**82385       32-bit Cache Controller for 80386               09/29/87...
**82385SX     32-bit Cache Controller for 80386SX             01/25/89...
**82395DX     High Performance Smart Cache                    06/18/90...
**82395SX     Smart Cache                                     12/17/90...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor  to form a CPU Cache chip  set designed for high
performance  servers  and   function-rich  desktops.  The  high  speed
interconnect between  the CPU and cache components  has been optimized
to  provide zero-wait  state operation.   This CPU  Cache chip  set is
fully compatible  with existing software,  and has new  data integrity
features for mission critical applications.

The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual  ported buffers and registers allow
the 82496  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit  wide memory bus widths,  16, 32, and 64  byte line sizes,
and optional sectoring.  The data path between the  CPU bus and memory
bus  is separated  by the  82491, allowing  the CPU  bus  to handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
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