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*Chips & Technologies...
**F87000   Multi-Mode Peripheral Chip                         11/23/93
***Info:
The F87000  Multi-Mode Peripheral  Chip is a  companion to  the F8680A
PC/CHIP single-chip PC. By strapping  pins to select the desired mode,
the F87000 device becomes one of four integrated peripheral chips that
extend the functionality of PC/CHIP.

Chips and Technologies, Inc. has designed the F87000 chip specifically
for use  with the F8680A  microchip to accommodate  portable computing
devices   and  embedded   control   applications  where   integration,
conservation of board space, and power consumption are critical.

In  PCMCIA  card  implementations,  card buffering  and  isolation  is
recommended for  design robustness,  especially in rugged  use enviro-
nments.  The buffering ensures that  the PCMCIA card receives a strong
clean  signal, while the  isolation provides  both the  protection for
"hot card insertion" and is hardwired for turning off power to a card.
Hardware isolation,  supported with Power  Management SuperState code,
minimizes the system’s power  consumption.  PCMCIA card slots that are
not properly buffered and isolated run  a high risk of a system crash/
failure if the cards are inserted/removed while the slot is powered.

The PC/CHIP F87000 is designed to be used in four modes. 
o    Mode 1 ---- Single PCMCIA card buffering support provides:
     • 20-bit address buffer.
     • 16-bit bidirectional data buffer.
     • Buffering for five control signals.
o    Modes 2 and 3 ---- Dual PCMCIA card buffering support provides:
     • Individual address buffering (64MB each).
     • Individual data bus buffering.
     • Two OR gates.
o    Mode 4 ---- Multifunctional mode provides:
     • Keyboard circuitry interfacing to a 16 x 8 keyboard matrix.
     • Clock divider conversion of 14.31818MHz to 1.8432MHz output 
       (divide by 7.77).
     • Parallel printer port.
     • IDE interface.
     • 7-bit configuration ports plus external select for port 
       expansion.

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*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91
***Notes:...
***Info:...
***Configurations:...
***Features:...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:
The HT18  is an advanced PC/AT compatible,  single-chip 80386SX design
solution. This  highly integrated single chip allows  simple, low cost
system  design options  while  featuring high  performance, low  power
consumption,  and minimum board  space requirements.   Advanced memory
management features  include support  for page mode,  with 2  or 4-way
interleaving  in both pipelined  and non-pipelined  modes(18A/B only).
Extended Hardware EMS  options include dual sets of  32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1,  1 by 4, and 1  by 9 device configurations. Rev  C supports 4M
devices, as well.  A Shadow RAM  option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT18 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows  for a  constant 8MHz  Bus clock  rate for  highest  bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin  Plastic Quad Flat  Pack combining several  external buffers
into this space saving solution.

***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
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