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**F87000   Multi-Mode Peripheral Chip                         11/23/93
***Info:...
***Versions:...
***Features:
o   Fully static design substantially reduces power consumption when 
    compared to discrete TTL designs, allowing direct battery drive.
o   3.3V or 5V operation provides flexibility for system design and 
    allows dynamic 3.3/5V switching of system voltage to further 
    reduce power consumption.
o   Each F8700 device can be strapped to configure one of three 
    buffer modes or a multi-function mode, reducing parts inventory 
    requirements.
o   High integration means each F8700 mode replaces at least seven 
    discrete TTL devices.
o   Full isolation of PCMCIA memory and I/O cards is supported to 
    allow safe insertion and removal of cards, both "hot" and "cold."
o   PCMCIA buffer modes are completely PCMCIA 2.0-compatible.
o   For single PCMCIA card support, Mode 1 buffers 20 address lines 
    and 5 control lines.  Because of the quiet bus design of PC/CHIPm 
    the upper address lines can be connected directly to the PCMCIA 
    card slot in a single card system for full 64MB support.
o   For dual PCMCIA card support, Modes 2 and 3 together buffer all 
    necessary address and control lines for independent 64MB support 
    of each card.
o   Between PCMCIA cycles, the F87000 sets PCMCIA buses and control 
    lines to a low-power state to consume only a fraction of the power 
    used in a standard TTL buffer design.
o   Multi-function mode (Mode 4) provides keyboard scanning, a 
    parallel interface, and IDE interface, a configuration latch, and 
    a 1.8MHz UART clock generation circuit.
o   Keyboard scan interface in the multi-function mode requires only a 
    single external resister pack and provides an interrupt to the 
    system on key depression. The interface can be used instead as 
    general-purpose 16-bit output and 8-bit input ports.
o   Parallel interface in the multi-functional mode allows high-speed,
    PS/2-compatible bidirectional communication with other systems.
o   Configuration latch can be used to control seven external devices 
    plus the UART clock divider. An additional decode line accommo-
    dates an external latch for eight more device control lines.

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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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