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**A note on VESA support of 486 chipsets.
Many chipsets state  that they support VESA local  bus.  In some cases
these actually  implement VLB somewhat  like PCI, where it  is entirly
decoupled from the CPU bus. Chipsets  that do not state they work with
VLB,  may  be found  on  motherboards  that  contain VLB  slots.   VLB
is  *basically*  The 486  CPU  pinout in  a  slot  form. Unless  these
m/boards contain  some additional  chips, there VLB  implementation is
directly coupled to the CPU.

**Datasheets:...
*_IBM...
*ACC Micro...
**ACC82021   Turbo PC/AT Chip Set (286/386SX 25MHz Max)            >88
***Notes:
The datasheet  for this chip set  only gives the general  section. The
2121  chip  has  a  separate  datasheet.  The  2000  and  2220  chip's
information is sourced from the ACC82020 datasheet.

The main difference between the  ACC82020 and the ACC82021 is that the
ACC82021  uses the  ACC2121  System/Memory controller  instead of  the
ACC2120.  

The  ACC2120 chip  lists some  features as  "Available fourth  quarter
1989". It would appear that nearly all the features listed in this way
are now in the ACC2121. Perhaps the ACC2120 chip was never updated and
instead replaced by the ACC2121.

Other features in the general section that differ are:

Differences:
Video BIOS shadowed
Lists Chip select for floppy instead of mouse


***info:...
***Configurations:...
***Features:...
**ACC82300   386 AT Chip Set (386DX)                               c88...
**ACC82C100  Single-Chip PC/XT Systems-Controller                  c90...
**ACC83000   Model 30 Integrated Chip Set (MCA)                    c88...
**ACC85000/A Model 50/60 Chipset (MCA)                             c88...
**ACC1000    Turbo PC/XT Integrated Bus and Peripheral Ctrl.  04/02/88...
**ACC2036    Single Chip Solution 2036 (286/386SX)              <Jul92...
**ACC2046/ST 486DX/486SX/386DX Single Chip AT                   <Jul92...
**ACC2048    WB 486 Notebook/Embedded Single Chip [no datasheet]     ?...
**ACC2051/NT PCI Single Chip Solution for Notebook Applications    c96...
**ACC2056    ?Pentium 3.3V Notebook               [no datasheet]<Jan96...
**ACC2057    PCI Notebook/Embedded Single Chip    [no datasheet]<Aug96...
**ACC2066NT  486 Notebook/Embedded Single Chip    [no datasheet]     ?...
**ACC2086    486 VL-based System Super Chip Soluti[no datasheet]     ?...
**ACC2087    Enhanced Super Chip (486 Single Chip)              <Aug96...
**ACC2089    486 PCI-based System Super Chip      [no datasheet]     ?...
**ACC2168/GT 32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2178A   32-bit 486 Green System Single Chip  [no datasheet]     ?...
**ACC2268    ?486                                 [no datasheet]     ?...
**ACC????    Maple/Maple-133 486-System-On-Chip   [no datasheet]     ?...
**
**Support Chips:
**ACC2016    Buffer and MUX Logic                                  c96...
**ACC2020    Power Management Chip                                 c92...
**ACC5500    Multifunction I/O Control Chip for PS2 Model 50/60    c88...
**
**Other chips...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
*Contaq  . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:...
***Configurations:...
***Features:
o   High Performance Second Level Cache
    - Zero Wait States at 66 MHz 
    - Two-Way Set Associative 
    - Writeback with MESI Protocol 
    - Concurrent CPU Bus and Memory Bus Operation 
    - Boundary Scan
o   Pentium Processor (735\90, 815\100)
    - Chip Set Version of Pentium Processor (735\90, 815\100) 
    - Superscalar Architecture
    - Enhanced Floating Point 
    - On-Chip 8K Code and 8K Data Caches
    - See Pentium Processor Family Data Book for More Information
o   Highly Flexible
    - 1 Mbyte to 2 Mbyte
    - 64-, or 128-Bit Wide Memory Bus
    - Synchronous, Asynchronous and Strobed Memory Bus Operation
    - Selectable Bus Widths, Line Sizes, Transfers and Burst Orders
o   Full Multiprocessing Support
    - Concurrent CPU, Memory Bus and Snoop Operations
    - Complete MESI Protocol
    - Internal/External Parity Generation/Checking
    - Supports Read For Ownership, Write-Allocation and Cache-to-Cache
      Transfers


**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...