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**82C100 IBM PS/2 Model 30/Super XT ?
***Info:...
***Configurations:...
***Features:...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82489DX Advanced Programmable Interrupt Controller 10/12/92
***Notes:...
***Info:
1.0 INTRODUCTION
The 82489DX Advanced Programmable Interrupt Controller provides
multiprocessor interrupt management, providing both static and dynamic
symmetrical interrupt distribution across all processors.
The main function of the 82489DX is to provide interrupt management
across all processors. This dynamic interrupt distribution includes
routing of the interrupt to the lowest-priority processor. The 82489DX
works in systems with multiple I/O subsystems, where each subsystem
can have its own set of interrupts. This chip also provides
inter-processor interrupts, allowing any processor to interrupt any
processor or set of processor. Each 82489DX I/O init interrupt input
pin is individually programmable by software as either edge or level
triggered. The interrupt vector and interrupt steering information an
be specified per pin. A 32-bit wide timer is provided that can be
programmed to interrupt the local processor. the timer can be used as
a counter to provide a time base to software running on the processor,
or to generate time slice interrupts locally to that processor. the
82489DX provides 32-bit software access to its internal
registers. Since no 82489DX register read have any side effects, the
82489DX registers can be aliased to a user read-only page for fast
user access (e.g., performance monitoring timers).
The 82489DX supports a generalized naming/addressing scheme that can
be tailored by software to fit a variety of system architectures and
usage models. It also supports 8259A compatibility by becoming
virtually transparent with regard to an externally connected 8259A
style controller, making the 8259A visible to software.
***Versions:...
***Features:...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**GCK181 Universal PS/2 Chip Set c:Mar89
***Info:
The GCK181 product family provides a universal engineering platform
for PS/2 compatible systems using the Intel 80286, 80386, and 80386SX
microprocessors. This chip set introduces the most highly integrated
solution for manufacturing high performance PS/2 compatible computer
systems.
The GC181 CPU/Bus Controller initiates and controls all bus cycles. It
controls the interface to the Micro Channel, address and data buffers,
CPU, DMA and Memory Controllers. Full Micro Channel support is
provided including Matched Memory Cycles and all timing requirements.
This device also integrates reset control and clock generation
logic. It is packaged in a 68 pin PLCC.
The GC182 Memory Controller interfaces the CPU and Micro Channel to
System DRAM. Four DRAM chip sizes are supported: lMxl, 1Mx4, 256kx1,
256Kx4. These can be configured to 8 MBytes of interleaved/paged
memory. Four memory modes are selectable to meet IBM Model 50/60/70/80
memory requirements. Zero wait state page mode is achievable at 20
MHz with 80ns DRAMs. Package type is 120 pin PQFP (plastic quad flat
pack).
The GC183 DMA Controller provides 8 DMA channels, supporting 24
address bits and 8 or 16 bit data transfers. This device provides the
Micro Channel with 15 levels of bus arbitration and support for
multiple bus masters. It also contains DRAM refresh logic and NPU
support logic. Package type is 160 pin PQFP.
The GC184 Address/Data Buffer integrates approximately 44 TTL packages
otherwise required in at P8/2 system. It is packaged in a 160 pin
PQFP.
The GC186 Peripheral Controller interfaces peripherals with the Micro
Channel. It supports 15 interrupt channels, the refresh rate counter,
and three programmable timers. It also contains PS/2 POS Registers, a
PS/2 and AT compatible parallel port, address decodes for serial
ports, floppy disk, keyboard, real time clock and CMOS RAM. Package
type is 160 pin PQFP
***Configurations:...
***Features:...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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