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**A note on VESA support of 486 chipsets.
Many chipsets state that they support VESA local bus. In some cases
these actually implement VLB somewhat like PCI, where it is entirly
decoupled from the CPU bus. Chipsets that do not state they work with
VLB, may be found on motherboards that contain VLB slots. VLB
is *basically* The 486 CPU pinout in a slot form. Unless these
m/boards contain some additional chips, there VLB implementation is
directly coupled to the CPU.
**Datasheets:...
*_IBM...
*ACC Micro...
*ALD...
*ALi...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**CS4041/5 CHIPSet (84041/84045) 2/10/95
***Info:
The CS4041 is the first product in the GreenCHIPS CHIPSet product
portfolio of Chips and Technologies, Inc. It provides all of the
system logic for implementing a high performance, Energy Star
compliant 486 PC/AT design, while maintaining an extremely competitive
cost structure. The powerful feature set includes the CHIPS "standard"
system blocks and offers a new level of system integration while
addressing the ever evolving requirements that the market place
demands. It is 100% PC/AT compatible and directly supports the 486DX,
486DX2, 486DX4, 486SX and 486 derivatives that support the CPU write
back cache architecture.
The high performance CHIPSet consists of the F84041 Systems Controller
and F84045 GreenCHIPS IPC. The F84041 System Controller is packaged in
a 208-pin PQFP and integrates the major system logic
functions. Included in the F84041 is the CHIPS patented Page
Interleave DRAM controller, high performance cache controller, VL
local bus controller, ISA bus controller, power management module, a
local bus IDE controller and fully compatible 8042 keyboard controller
with PS/2 mouse support. The companion F84045 is packaged in a 100 pin
PQFP and contains the industry standard Integrated Peripheral
Controller (IPC) which includes the DMA controllers, timers, interrupt
controllers and real time clock.
The enhanced feature set of GreenCHIPS DRAM and cache controllers are
perfect for today's High Performance PC/AT designs. The page
interleave DRAM controller offers high performance as well as extreme
flexibility in supporting 486 memory subsystems. The DRAM controller
supports up to eight banks of memory that can be configured with 256K,
1M, 4M or 16M memory devices. Page interleaving, timing modes, memory
mix options, direct drive support and block by block parity support
can be tuned to meet the most optimum requirements for the system
design. In addition, the high performance secondary cache controller
provides options that can be optimized for performance, cost or
both. The direct mapped cache architecture employs internal
comparators with external TAG and data SRAM that can operate in a
write-through or write-back mode. Cache sizes from 64K to 1M are
supported with flexible single bank or dual bank support that allow
flexible timing mode selection based on CPU speed and SRAM speed.
The "Green" in GreenCHIPS comes from the Power management support
integrated in the CHIPSet. The CS4041 provides the perfect level of
power management support for Energy Star compliant desktops. Included
in the power management section is direct support for SMM operation
and clock switching for the popular 486 derivatives. Two event timers,
programmable I/O pins, I/O restart and programmable event detection
provide a wide range of options for power management selection and
customization.
The CS4041 provides new levels of integration in system logic CHIPSets
by providing a local bus IDE interface and keyboard controller. The
robust local bus IDE interface is decoupled from the AT state machine
and does not use a VL local bus load. The interface is versatile
enough to support up to eight IDE drives allowing each drive to have
unique command settings. The result is the best performance for each
drive type allowing significant performance gains over the standard
ISA interface. This is accomplished without any compromise to the
standard VL local bus.
CPUs Supported
oIntel 486 CPUs
oAMD 486 CPUs
oCyrix 486 CPUs
oIBM 486 CPUs
oL1 (CPU) write back cache fully supported
oSMI support (both Intel and Cyrix)
oClock Frequencies:
25MHz, 33MHz, 40MHz, 50MHz
***Configurations:...
***Features:...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82485 Turbo Cache (and 485Turbocache) c90
***Notes:...
***Info:
The 82485 is a second-level cache controller designed to improve the
performance of Intel486 Microprocessor systems. One 82485 cache
controller supports 64K or 128K bytes of second level cache memory
that maps to the entire 4 Gigabytes of the Intel486 microprocessor
address space. The controller is completely software transparent. One
controller plus SRAMs provides a 64K or a 128K cache. External EPROM
can be cached yet remain write protected. The 82485 is fully
compatible with the Intel486 microprocessor. All Intel486 CPU bus
cycles and timings are supported.
A complete, optional second level cache controller using the 82485 is
available as the 485Turbocache Module from Intel (data sheet order
number 240722).
2.0 FUNCTIONAL DESCRIPTION
2.1 Introduction
The 82485 is a single ported, two-way set associative cache controller
designed specifically to interface with the Intel486 microprocessor.
The controller supports either a sectored configuration (two lines per
tag) or a non-sectored configuration (one line per tag). The 82485
will directly support a nonsectored 64K data cache or a 128K sectored
data cache. Both the 64K and 128K configurations are able to map the
entire 4 gigabytes of the Intel486 microprocessor address space. The
82485 interfaces directly to the Intel486 microprocessor. All Intel-
486 CPU bus cycles and timings are supported. The 82485 also supports
0 wait state processor operation when there is a cache hit and has
provisions to support invalidation cycles, BOFF# cycles, and premature
BLAST# terminations. The controller is look aside (monitors bus act-
ivity in parallel to the processor) and write through (all writes pro-
pagate to the system bus), so it supports the same cache consistency
mechanisms as the Intel486 CPU. The controller also provides a safe
method to cache ROM BIOS through the use of a write protect pin and a
write protect strapping option.
The data cache (Static RAM) resides external to the 82485. The 82485
provides all controls for the SRAMs. No external latches or tran-
ceivers are required. The 82485 output buffers support up to eight
SRAMs. A 64K cache can be designed with only five components; nine
components for a 128K cache. Two-way set associativity is provided by
dual banked SRAMs. Data parity is supported.
The 82485 can be used to design a custom second level cache
configuration. For an easier system design and higher integration, the
82485M Turbocache can be used (see data sheet order number 240722).
This module is a complete second level cache in one package. It
consists of a single 82485 cache controller and SRAM to provide a
complete 64K or 128K second level Intel486 microprocessor second level
cache.
***Versions:...
***Features:...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
*ZyMOS...
*General Sources:...
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