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**M1531/33/43 Aladdin IV & IV+ 50-83.3MHz <05/28/97
***Info:...
***Configurations:...
***Features:
****M1531 CPU-to-PCI bridge, Memory, Cache and Buffer Controller:...
****M1533 PCI-to-ISA Bus Bridge:...
**M1541/42/33/43 Aladdin V & V+ 50-100MHz ?...
**M1561/43/35D Aladdin 7 ArtX [no datasheet, some info] 11/08/99...
**M6117 386SX Single Chip PC <97...
**
**Support Chips:
**M1535/D South Bridge ?...
**
**May not exist:...
**Later Chipsets:...
**Other:...
*AMD . . . . . . . [no datasheets, some info]...
*Chips & Technologies...
**CS4041/5 CHIPSet (84041/84045) 2/10/95
***Info:...
***Configurations:...
***Features:...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:
The 82496 Cache Controller and multiple 82491 Cache SRAMs combine with
the Pentium processor to form a CPU Cache chip set designed for high
performance servers and function-rich desktops. The high speed
interconnect between the CPU and cache components has been optimized
to provide zero-wait state operation. This CPU Cache chip set is
fully compatible with existing software, and has new data integrity
features for mission critical applications.
The 82496 cache controller implements the MESI write-back protocol for
full multiprocessing support. Dual ported buffers and registers allow
the 82496 to concurrently handle CPU bus, memory bus, and internal
cache operation for maximum performance.
The 82491. is a customized high-performance SRAM that supports 32, 64,
and 128-bit wide memory bus widths, 16, 32, and 64 byte line sizes,
and optional sectoring. The data path between the CPU bus and memory
bus is separated by the 82491, allowing the CPU bus to handshake
synchronously, asynchronously, or with a strobed protocol, and
allowing concurrent CPU bus and memory bus operations.
***Configurations:...
***Features:...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
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