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*Chips & Technologies...
**CS8238 CHIPS/280 & 281 (386 MCA)(82C321/322/325/223/226) c:Aug89
***Info:...
***Configurations:
Technically the CS8238 != CHIPS/280. The CS8238 consists of:
82C321 (CPU/Bus Controller)
82C322 (DRAM Controller)
82C325 (Data Buffers)
82C223 (DMA Controller)
82C226 (System Peripheral Controller)
The CHIPS/280 consists of the CS8238 and:
82C607 Multi-Function Controller
82C451/452 VGA chip
The 82C322 DRAM Controller can be extended to support the EMS 4.0
using:
82C631 EMS mapper chip
According to page 34 of:
https://ia801909.us.archive.org/9/items/bitsavers_chipsAndTew_4887212/PS2_Chipset_Overview.pdf
The CHIPS/280 is for 16, 20 MHz, the CHIPS/281 is for 20, 25 MHz.
***Features:...
**CS82310 PEAK/DM 386 AT (82C351/82C355/82C356) c91...
**CS8281 NEATsx (386SX) (82C811/812/215/206) c:Dec89...
**CS8283 LeAPset-sx (82C841/82C242/82C636) c:Mar90...
**CS8285 PEAKsx (82C836/82C835) c91...
**CS8288 CHIPSlite-sx (82C836/82C641/82C835) c?...
**CS4000 WinCHIPS (64200/84021/84025) c92...
**CS4021 ISA/486 (84021/84025) c92...
**CS4031 CHIPSet (84031/84035) 5/10/93...
**CS4041/5 CHIPSet (84041/84045) 2/10/95...
**CB8291 ELEAT [no datasheet] c90...
**CB8295 ELEATsx [no datasheet] c90...
**82C100 IBM PS/2 Model 30/Super XT ?...
**82C110 IBM PS/2 Model 30/Super XT ?...
**82C235 Single Chip AT (SCAT) c89...
**82C836 Single Chip 386sx (SCATsx) <91...
**F8680/A PC/CHIP Single-Chip PC c93...
**
**Support Chips:
**64200 (Wingine) High Performance 'Windows Engine' c:Oct91...
**82C206 Integrated Peripheral Controller c86...
**82C601/A Single Chip Peripheral Controller <08/30/90...
**82C607 Multifunction Controller <Jun88...
**82C710 Universal Peripheral Controller c:Aug90...
**82C711 Universal Peripheral Controller II c:Jan91...
**82C712 Universal Peripheral Controller II c:Jan91...
**82C721 Universal Peripheral Controller III c:May93...
**82C735 I/O Peripheral Controller With Printgine c:Jul93...
**82C835 Single CHIP 386sx AT Cache Controller c:Apr91...
**F87000 Multi-Mode Peripheral Chip 11/23/93...
**Other:...
**Disk:...
**Video:...
*Contaq . . . . . [no datasheets, some info]...
*Efar Microsystems [no datasheets, some info]...
*ETEQ...
*Faraday...
*Forex . . . . . . [List only, no datasheets found]...
*Intel...
**450NX (?) 06/29/98:
Chips:
[82454NX] (PXB) [82453NX] (MUX)
[82452NX] (RCG) [82451NX] (MIOC)
[82371EB] (PIIX4E),
CPUs: Single/Dual/Quad P-II Xeon/P-III Xeon
DRAM Types: FPM EDO 2-way Interleave 4-way Interleave
Mem Rows: 8
DRAM Density: 16Mbit 64Mbit
Max Mem: 8GB
ECC/Parity: Both
AGP speed: N/A
Bus Speed: 100
PCI Clock/Bus: 1/3
**????? (Profusion) c:99...
**800 series...
*Headland/G2...
**GCK181 Universal PS/2 Chip Set c:Mar89
***Info:
The GCK181 product family provides a universal engineering platform
for PS/2 compatible systems using the Intel 80286, 80386, and 80386SX
microprocessors. This chip set introduces the most highly integrated
solution for manufacturing high performance PS/2 compatible computer
systems.
The GC181 CPU/Bus Controller initiates and controls all bus cycles. It
controls the interface to the Micro Channel, address and data buffers,
CPU, DMA and Memory Controllers. Full Micro Channel support is
provided including Matched Memory Cycles and all timing requirements.
This device also integrates reset control and clock generation
logic. It is packaged in a 68 pin PLCC.
The GC182 Memory Controller interfaces the CPU and Micro Channel to
System DRAM. Four DRAM chip sizes are supported: lMxl, 1Mx4, 256kx1,
256Kx4. These can be configured to 8 MBytes of interleaved/paged
memory. Four memory modes are selectable to meet IBM Model 50/60/70/80
memory requirements. Zero wait state page mode is achievable at 20
MHz with 80ns DRAMs. Package type is 120 pin PQFP (plastic quad flat
pack).
The GC183 DMA Controller provides 8 DMA channels, supporting 24
address bits and 8 or 16 bit data transfers. This device provides the
Micro Channel with 15 levels of bus arbitration and support for
multiple bus masters. It also contains DRAM refresh logic and NPU
support logic. Package type is 160 pin PQFP.
The GC184 Address/Data Buffer integrates approximately 44 TTL packages
otherwise required in at P8/2 system. It is packaged in a 160 pin
PQFP.
The GC186 Peripheral Controller interfaces peripherals with the Micro
Channel. It supports 15 interrupt channels, the refresh rate counter,
and three programmable timers. It also contains PS/2 POS Registers, a
PS/2 and AT compatible parallel port, address decodes for serial
ports, floppy disk, keyboard, real time clock and CMOS RAM. Package
type is 160 pin PQFP
***Configurations:...
***Features:...
**HT11 Single 286 AT Chip [no datasheet] <Aug90...
**HT12/+/A Single 286 AT Chip with EMS support c:Aug90...
**HT18 80386SX Single Chip c:Sep91...
**HT21 386SX/286 Single Chip (20 MHz) c:Aug91...
**HT22 386SX/286 Single Chip (25 MHz) c:Sep91...
**HT25 3-volt Core Logic for 386SX c:Dec92...
**HT35 Single-Chip Peripheral Controller [partial info] ?...
**HTK320 386DX Chip Set c:Sep91...
**HTK340 "Shasta" 486 Chip Set c:Jun92...
**Support Chips:
**HT44 Secondary Cache c:Jun92...
**Other:...
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