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**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91
***Notes:...
***Info:
The Intel 82495XP cache controller and 82490XP cache RAM, when coupled
with a user-implemented memory  bus controller, provide a second-level
cache  subsystem  that eliminates  the  memory  latency and  bandwidth
bottleneck for  a wide  range of multiprocessor  systems based  on the
i860 XP  microprocessor. The CPU  interface is optimized to  serve the
i860  XP microprocessor  with zero  wait  states at  up to  50 MHz.  A
secondary cache  built from the  82495XP and 82490XP isolates  the CPU
from  the memory subsystem;  the memory  can run  slower and  follow a
different protocol than the i860 XP microprocessor.
         
***Features:...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
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***Notes (Unverified Information!):...
***5600        c:Nov98...
***600         ?...
***620         c:Apr99...
***621         ?...
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***635/635T    c:Mar01...
***640T        c:Mar01      ...
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**W860551/P UART with FIFO and Printer Port Controller             <94
***Info:...
***Versions:...
***Features:
o  Easily interfaces with most popular microprocessors
o  Pin compatible and functionally compatible with the existing 
   W860451
o  Centronics parallel interface
o  Capable of running all existing 16450 and 16550 software
o  Uses system's 14.3181 BMHz clock input
o  In FIFO mode transmitter and receiver are each buffered with 
   16-byte FIFOs to reduce number of intercepts presented to the CPU
o  Adds or deletes standard asynchronous communication bits (start, 
   stop, and parity) to or from serial data
o  Independently controlled transmit, receive, line status, and data 
   set interrupts
o  Programmable baud rate generator
o  Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
o  Fully programmable serial-interface characteristics:
   - 5, 6, 7, or 8-bit characters
   - Even, odd, or no-parity bit generation and detection
   - 1, 1.5, or 2-stop bit generation
   - Baud generation
o  False start bit detection
o  Internal diagnostic capabilities:
   - Loopback controls for communications link fault isolation
   - Break, parity, overrun, framing error simulation
o  Fully prioritized interrupt system controls
o  40-pin PDIP package for W860551 and 44-pin PLCC package for 
   W86C551P

**
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