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**82395SX     Smart Cache                                     12/17/90
***Notes:...
**82396SX     Smart Cache                                     12/17/90...
**82485       Turbo Cache (and 485Turbocache)                      c90...
**82489DX       Advanced Programmable Interrupt Controller    10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set                           <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860)       06/05/91...
**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
**HT18          80386SX Single Chip                            c:Sep91
***Info:
The HT18  is an advanced PC/AT compatible,  single-chip 80386SX design
solution. This  highly integrated single chip allows  simple, low cost
system  design options  while  featuring high  performance, low  power
consumption,  and minimum board  space requirements.   Advanced memory
management features  include support  for page mode,  with 2  or 4-way
interleaving  in both pipelined  and non-pipelined  modes(18A/B only).
Extended Hardware EMS  options include dual sets of  32 registers with
multiple context operation. Revisions A/B support 256K and 1M DRAMs in
1 by 1,  1 by 4, and 1  by 9 device configurations. Rev  C supports 4M
devices, as well.  A Shadow RAM  option for System Video BIOS and dual
or single system ROM BIOS support adds to overall design versatility.

A  complete PC/AT  compatible  system with  advanced  features may  be
implemented with minimal external support logic. The HT18 performs all
CPU  and peripheral support  functions in  a single  chip.  Integrated
device  functions include  DMA Controllers,  a Memory  Mapper, Timers,
Counters, Interrupt  Controllers, a Bus Controller  and all supporting
circuitry for PC core logic requirements. An asynchronous AT Bus clock
allows  for a  constant 8MHz  Bus clock  rate for  highest  bus device
compatibility as defined in IEEE Spec P996. This device is packaged in
a 208-pin  Plastic Quad Flat  Pack combining several  external buffers
into this space saving solution.

***Configurations:...
***Features:...
**HT21          386SX/286 Single Chip (20 MHz)                 c:Aug91...
**HT22          386SX/286 Single Chip (25 MHz)                 c:Sep91...
**HT25          3-volt Core Logic for 386SX                    c:Dec92...
**HT35          Single-Chip Peripheral Controller [partial info]     ?...
**HTK320        386DX Chip Set                                 c:Sep91...
**HTK340        "Shasta" 486 Chip Set                          c:Jun92...
**Support Chips:
**HT44          Secondary Cache                                c:Jun92...
**Other:...
*HMC (Hulon Microelectronics)...
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*OPTi...
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*Symphony...
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*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W860551/P UART with FIFO and Printer Port Controller             <94
***Info:...
***Versions:...
***Features:
o  Easily interfaces with most popular microprocessors
o  Pin compatible and functionally compatible with the existing 
   W860451
o  Centronics parallel interface
o  Capable of running all existing 16450 and 16550 software
o  Uses system's 14.3181 BMHz clock input
o  In FIFO mode transmitter and receiver are each buffered with 
   16-byte FIFOs to reduce number of intercepts presented to the CPU
o  Adds or deletes standard asynchronous communication bits (start, 
   stop, and parity) to or from serial data
o  Independently controlled transmit, receive, line status, and data 
   set interrupts
o  Programmable baud rate generator
o  Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
o  Fully programmable serial-interface characteristics:
   - 5, 6, 7, or 8-bit characters
   - Even, odd, or no-parity bit generation and detection
   - 1, 1.5, or 2-stop bit generation
   - Baud generation
o  False start bit detection
o  Internal diagnostic capabilities:
   - Loopback controls for communications link fault isolation
   - Break, parity, overrun, framing error simulation
o  Fully prioritized interrupt system controls
o  40-pin PDIP package for W860551 and 44-pin PLCC package for 
   W86C551P

**
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