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**82496/491     Cache Controller / Cache RAM (for P5 Pentium) 03/22/93
***Notes:...
***Info:...
***Configurations:...
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**82497/492   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94...
**
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**450NX  (?)            06/29/98:...
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**SL82C460   'Haydn II' 80486 chipset   [no datasheet]         c:Jun91
***Notes:
from:
http://www.cbronline.com/news/symphony_introduces_the_haydn_family

"Santa Clara, California-based  Symphony Laboratories Inc has unvieled
a family  of highly integrated core  logic chip sets for  all forms of
AT-alike personal  computers: the Haydn family  comprises the SL82C460
set for  80486 systems and the  SL82C360 set for  80386 machines; each
set includes two devices, a system controller and a bus controller and
an optional cache controller chip  can be added if cache capability is
required;  the   parts  are  in  volume  production   and  a  complete
motherboard can be created with as few as eight active components plus
memory; all operate at 50MHz and  beyond and the sets are supported by
all  major BIOS  vendors; the  sets cost  from $50  to $100  apiece in
quantities of 100-up."

***Configurations:...
**SL82C470   'Mozart' 486/386 EISA chipset                     c:Dec91...
**SL82C490   'Wagner' 486?              [no datasheet]               ?...
**SL82C550   'Rossini' Pentium          [no datasheet]            c:95...
**
**Support Chips:
**SL82C365    Cache Controller (for 386DX/SX)                     c:91...
**SL82C465    Cache Controller (for 486/386DX/SX)                 c:91...
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**W86C452   I/O controller for IBM PC/AT                         Jul89
***Info:
GENERAL DESCRIPTION

The W86C452 is an enhanced dual-channel version of the popular W86C450
asynchronous  communication element  (ACE) fabricated  using WINBOND'S
CMOS process.  It is  equivalent to VL160452  of the  VLSI Technology
Inc.

The  device   supports  two  serial-to-parallel   conversion  on  data
characters  received  from  a  peripheral  device  or  a  MODEM.   and
parallel-to-serial  conversion on  data characters  received  from the
CPU.

The CPU  can read the complete status  of the UART at  any time during
the  functional operation.  Status  information reported  includes the
type and condition  of the transfer operations being  performed by the
UART as  well as  any error conditions  (parity. overrun,  framing, or
break interrupt).

The UART includes  a programmable baud rate generator  that is capable
of dividing the timing reference clock input by divisors of l to (2^16
-1), and  producing a 16 x  clock for driving  the internal transmiter
logic. Provisions  are also included to  use this 16 x  clock to drive
the  receiver  logic.   The  UART includes  a  complete  MODEM-control
capability  and  a  processor-interrupt  system.   Interrupts  can  be
programmed  to  the  user’s  requirements,  minimizing  the  computing
required to handle the communications link.

In addition  to its communication interface  capabilities, the W86C452
provides the user with  a fully bidirectional parallel Centronics type
printer.  This part  allows  information received  from either  serial
communication port to be printed from the dual ACE.

***Versions:...
***Features:...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
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