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**82498/493   Cache Controller / Cache RAM (for P54 Pentium)    <Nov94
***Notes:...
***Info:
The 82498 Cache Controller and multiple 82493 Cache SRAMs combine with
the Pentium processor (735/90,  815/100) and future Pentium Processors
to form a CPU Cache chip set designed for high performance servers and
function-rich  desktops. The high-speed  interconnect between  the CPU
and  cache components has  been optimized  to provide  zero-wait state
operation. This CPU  Cache chip set is fully  compatible with existing
software,  and has new  data integrity  features for  mission critical
applications.

The 82498 Cache Controller implements the MESI write-back protocol for
full multiprocessing support.  Dual ported buffers and registers allow
the 82498  to concurrently  handle CPU bus,  memory bus,  and internal
cache operation for maximum performance.

The 82493 is a customized high-performance SRAM that supports 64-, and
128-bit  wide memory  bus widths,  32-,  and 64-byte  line sizes,  and
optional sectoring. The  data path between the CPU  bus and memory bus
is  separated  by  the  82493,  allowing  the  CPU  bus  to  handshake
synchronously,  asynchronously,  or   with  a  strobed  protocol,  and
allowing concurrent CPU bus and memory bus operations.

***Configurations:...
***Features:...
**
**Later chipsets (basic spec):
**440 series:...
**450NX  (?)            06/29/98:...
**?????  (Profusion)    c:99...
**800 series...
*Headland/G2...
*HMC (Hulon Microelectronics)...
*Logicstar...
*Motorola...
*OPTi...
**82C596/597     PTMAWB Pentium Adaptive Write-back (Cobra)       c:93
***Notes::...
***Info:...
***Configurations:...
***Features:...
**82C650/1/2     Discovery (Pentium Pro) [no datasheet]              ?...
**82C681/2/6/7   386/486WB EISA                                   c:92...
**82C683         386/486AWB EISA [no datasheet]                      ?...
**82C693/6/7     Pentium uP Write Back Cache EISA                 c:93...
**82C700         FireStar                                         c:97...
**82C701         FireStar Plus                                    c:97...
**82C750         Vendetta      [no datasheet]                        ?...
**82c801         SCWB2 DX Single Chip Solution                    c:92...
**82C802         SCWB2 PC/AT Single Chip [no datasheet]              ?...
**82C802G/GP     System/Power Management Controller (cached)      c:93...
**82C895         System/Power Management Controller (cached)   c:Sep94...
**82C898         System/Power Management Controller (non-cache)c:Nov94...
**
**Support Chips:
**82C601/2       Buffer Devices                                 <Nov94...
**82C822         PCIB (VLB-to-PCI bridge)                         c:94...
**Other:...
*PC CHIPS/Amptron/Atrend/ECS/Elpina/etc...
*SIS...
*Symphony...
*TI (Texas Instruments)...
*UMC...
*Unresearched:...
*VIA...
*VLSI...
*Western Digital...
*Winbond...
**W86C452   I/O controller for IBM PC/AT                         Jul89
***Info:
GENERAL DESCRIPTION

The W86C452 is an enhanced dual-channel version of the popular W86C450
asynchronous  communication element  (ACE) fabricated  using WINBOND'S
CMOS process.  It is  equivalent to VL160452  of the  VLSI Technology
Inc.

The  device   supports  two  serial-to-parallel   conversion  on  data
characters  received  from  a  peripheral  device  or  a  MODEM.   and
parallel-to-serial  conversion on  data characters  received  from the
CPU.

The CPU  can read the complete status  of the UART at  any time during
the  functional operation.  Status  information reported  includes the
type and condition  of the transfer operations being  performed by the
UART as  well as  any error conditions  (parity. overrun,  framing, or
break interrupt).

The UART includes  a programmable baud rate generator  that is capable
of dividing the timing reference clock input by divisors of l to (2^16
-1), and  producing a 16 x  clock for driving  the internal transmiter
logic. Provisions  are also included to  use this 16 x  clock to drive
the  receiver  logic.   The  UART includes  a  complete  MODEM-control
capability  and  a  processor-interrupt  system.   Interrupts  can  be
programmed  to  the  user’s  requirements,  minimizing  the  computing
required to handle the communications link.

In addition  to its communication interface  capabilities, the W86C452
provides the user with  a fully bidirectional parallel Centronics type
printer.  This part  allows  information received  from either  serial
communication port to be printed from the dual ACE.

***Versions:...
***Features:...
**W86C456   I/O controller [no datasheet]                            ?
**W860551/P UART with FIFO and Printer Port Controller             <94...
**
**Other:...
*ZyMOS...
*General Sources:...