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**82395SX Smart Cache 12/17/90
***Notes:...
**82396SX Smart Cache 12/17/90...
**82485 Turbo Cache (and 485Turbocache) c90...
**82489DX Advanced Programmable Interrupt Controller 10/12/92...
**82495DX/490DX DX CPU-Cache Chip Set <Sep91...
**82495XP/490XP Cache Controller / Cache RAM (for i860) 06/05/91...
**82496/491 Cache Controller / Cache RAM (for P5 Pentium) 03/22/93...
**82497/492 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**82498/493 Cache Controller / Cache RAM (for P54 Pentium) <Nov94...
**
**Later chipsets (basic spec):
**440 series:...
**450NX (?) 06/29/98:...
**????? (Profusion) c:99...
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*Headland/G2...
**HT44 Secondary Cache c:Jun92
***Info:...
***Versions:...
***Features:
General Features
o Support for 4868X/DX/DX2 CPUs
o System implementation with Headland’s HTK340 chip set and future
486 chip sets
o 16, 20, 25 and 33 MHz CPU speeds
Memory Configurations
o 32KB, 64KB, 128KB, 256KB, 512KB & 1MB cache sizes
o 25ns SRAMs required at 33 MHz
o Asynchronous and synchronous SRAMs are supported
o Programmable write-protected and non-cacheable regions are
supported through the chip set
Architecture
o Look-Aside
o Write through
o Direct mapped
o Integrated tag comparator
o Zero wait state cache hits
o Simultaneous 486 and secondary cache update on read miss
o 486 line burst cycle support
Package & Die
o 84-pin PLCC
o LSI Logic’s 0.7 micron HCMOS process
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*Unresearched:...
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*Winbond...
**W86C452 I/O controller for IBM PC/AT Jul89
***Info:
GENERAL DESCRIPTION
The W86C452 is an enhanced dual-channel version of the popular W86C450
asynchronous communication element (ACE) fabricated using WINBOND'S
CMOS process. It is equivalent to VL160452 of the VLSI Technology
Inc.
The device supports two serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM. and
parallel-to-serial conversion on data characters received from the
CPU.
The CPU can read the complete status of the UART at any time during
the functional operation. Status information reported includes the
type and condition of the transfer operations being performed by the
UART as well as any error conditions (parity. overrun, framing, or
break interrupt).
The UART includes a programmable baud rate generator that is capable
of dividing the timing reference clock input by divisors of l to (2^16
-1), and producing a 16 x clock for driving the internal transmiter
logic. Provisions are also included to use this 16 x clock to drive
the receiver logic. The UART includes a complete MODEM-control
capability and a processor-interrupt system. Interrupts can be
programmed to the user’s requirements, minimizing the computing
required to handle the communications link.
In addition to its communication interface capabilities, the W86C452
provides the user with a fully bidirectional parallel Centronics type
printer. This part allows information received from either serial
communication port to be printed from the dual ACE.
***Versions:...
***Features:...
**W86C456 I/O controller [no datasheet] ?
**W860551/P UART with FIFO and Printer Port Controller <94...
**
**Other:...
*ZyMOS...
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